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JESD204B (Agilex F-Tile) v1.0.0 - Support Logic Generation Error (Quartus 22.1)

waterst
Beginner
357 Views

Hi there,

I've recently upgraded to Quartus 22.1 to enable generation of the JESD204B IP for Agilex F-Tile devices. Following IP customisation, I am able to perform the 'Generate HDL' step but the example design generation fails. Generating the IP with the default JESD204B parameters or various non-default sets in transmitter/receiver/duplex modes all fail. 

 

Digging into the problem a bit further, it appears that the logic generation process is failing - this is repeatable if I try this through the Quartus GUI or by running quartus_tlg from the command line. The error is as follows:

Error (21842): Support logic cannot be generated because IP components used in the design have conflicting settings

Note: this is a clean project which only contains a single instance of the JESD204B IP. 

 

This issue looks similar to one which affected the SDI II Intel Agilex F-Tile FPGA IP design example:

https://www.intel.com/content/www/us/en/support/programmable/articles/000088714.html

The release notes for 22.1 don’t state whether this issue has been resolved or not and whether it is isolated to the SDI II IP. I haven’t tried applying the supplied patch as it appears to be specific to version 21.4.

 

I note from the previous JESD204B example design user guide (for 21.3) that preset IP parameters should be selected in order to generate the example design but the 22.1 IP GUI doesn't have any preset by default. 

 

Any thoughts on what the cause might be. Is this an issue with the 22.1 release?

 

Many thanks,
Toby

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1 Solution
ZulsyafiqH_Intel
Employee
290 Views

Hi Toby,


Good day.

Thank you for your patience.


>Is this an issue with the 22.1 release?

At the moment, there is no known issue such as the error(21842).

We have tried with Intel® Quartus® Prime Software version 22.1 from our side but did not manage to replicate the error.


We suggest you to try generate our design example as per the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide to see if this error still happen.


If the error still occur, please do attach your design here for us to have a look.


Thank you.


Best Regards,

ZulsyafiqH_Intel


View solution in original post

8 Replies
ZulsyafiqH_Intel
Employee
328 Views

Hi Toby,


Currently we are confirming the details with our internal team.

We will get back to you as soon as possible.


Thank you.


Best Regards,

Zul


waterst
Beginner
322 Views

Hi Zul, 

 

Thanks for picking this up. Please let me know if you require any further details. 

 

Kind regards,
Toby

ZulsyafiqH_Intel
Employee
291 Views

Hi Toby,


Good day.

Thank you for your patience.


>Is this an issue with the 22.1 release?

At the moment, there is no known issue such as the error(21842).

We have tried with Intel® Quartus® Prime Software version 22.1 from our side but did not manage to replicate the error.


We suggest you to try generate our design example as per the JESD204B Intel® Agilex™ FPGA IP Design Example User Guide to see if this error still happen.


If the error still occur, please do attach your design here for us to have a look.


Thank you.


Best Regards,

ZulsyafiqH_Intel


waterst
Beginner
268 Views

Hi Zul,

 

Looks like the comments about support logic generation above were not relevant. This issue is specifically related to the example design generation failure. My colleague has been able to replicate this on Windows using the 22.1 'Complete Download' (I used the 'Individual Files'). I can confirm that this works correctly under Linux so this issue appears to be specific to Windows. 

 

The design example user guide that you posted is for the E-Tile version of the IP and doesn't appear to have been updated for the F-Tile variant. Do you know if there is a separate document to cover this?

 

We are still looking for a resolution to this as our development team is using Windows. Is it possible to clear the accepted solution on this post as it has not been resolved?

 

Thanks,
Toby

ZulsyafiqH_Intel
Employee
289 Views

Hi Toby,

 

Below is the design example user guide link:

JESD204B Intel® Agilex™ FPGA IP Design Example User Guide 

 

Thank you.

 

Best Regards,

ZulsyafiqH_Intel

ZulsyafiqH_Intel
Employee
209 Views

Hi Toby,


Good Day.

Apologize for the delayed response.

Due to some the technical error, we have just receive your reply.


>Do you know if there is a separate document to cover this?

I'm afraid that we only have1 User Guide for Agilex at the moment.


>Is it possible to clear the accepted solution on this post as it has not been resolved?

I have tried to remove it but I cannot due to system limitation.

After further discussion with internal team, it is found that I can only change the accepted solution but not remove it. Hence, once we have come to the final solution, I will change it.


May I know your Agilex F-Tile device type? The product variant?

So that I can create a sample Example Design from my side for you to test on your side.


Thank you.


Best Regards,

ZulsyafiqH_Intel


ZulsyafiqH_Intel
Employee
192 Views

Hi Toby,


Did you get my update on my previous reply?


Thank you.


Best Regards,

ZulsyafiqH_Intel


ZulsyafiqH_Intel
Employee
179 Views

Hi Toby,


We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


Thank you.


Best Regards,

ZulsyafiqH_Intel


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