for TI AFE58JD48, total16 ADCs, 8 JESD204B Lane, for each chip has two die share 16 ADCs and 8 lanes. I plan to only use 4 lanes for 16 ADC channels, for each die LMF == 2(lanes), 8(ADC channel), 8( octets per frame). For each chip has to set two dies separately.
if we are going to use total 4 AFE58, total 64 ADC channels divided by 8 dies, for receive side, if the FPGA set to 16 lanes. will it work if I set LMF == 16 (lanes), 64(ADC channels), 8 ( octets per frame)?