JESD204B Latency Issue – Sample Shift Observed

[suleman]

Hi All,

We are using a JESD204B IP core (Subclass 1) to receive trigger-synchronized data from an ADC. After every power cycle or reconfiguration, the lane alignment results in different latency.

After each power cycle or reconfiguration, we observe a shift in the ADC samples. Sometimes it's 1 sample, sometimes 3, and it can go up to 8 samples.

I hope someone can help me with this issue to find out potential causes for this behavior and suggest ways to resolve or mitigate it? Can we know this latency, how to reduce this latency.

Setup:

JESD204B Configuration:

L=4, M=1, F=2, S=4 and K=16.

Subclass 1 with continuous SYSREF.

The IOPLL compensation mode is set to "source synchronous"

[RongYuan]

Hi,

May I know which FPGA(and T-tile) and Quartus version?

Thanks,

Rong

[suleman]

Hi @RongYuan ,

My apologies for late response.

Following are the details you asked.

FPGA: Intel Arria-10 (10AX048H3F34E2LG)

T-Tile: 

Lanes: RX Four Lane

RX_0:

Channel: IOIBUF_X0_Y37_N112

PIN: AC30

RX_1:

Channel: IOIBUF_X0_Y35_N112

PIN: AB32

RX_2:

Channel: IOIBUF_X0_Y34_N112

PIN: AA30

RX_3:

Channel: IOIBUF_X0_Y33_N112

PIN: Y32

I/O Bank: 1D

Quartus: Std vq18.1

Thanks