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Altera_Forum
Honored Contributor I
928 Views

JTAG UART receive Integers from FPGA

Dear community, 

 

I'm trying to send some initialisation data to the FPGA and receive the results via JTAG UART. 

 

The problem is that nios2-terminal, which I'm using to communicate with the JTAG UART IP core is text based, but I want to send and receive integers. 

 

So I redirected StdIn and StdOut of nios2-terminal to my program and I send single Bytes to nios2-terminal. 

Its a little tricky because when I send the byte 0x00 it terminates the string and the following bytes are all zero. So I wait after 0x00 until the Buffer is empty, which should be instantly because the FPGA should read much faster than I can write, but idk... 

But except this problem, every byte I write to the nios2-terminal arrives at the FPGA without any losses or adding of bytes. Or maybe it does but not with the bytes in my initialisation data. 

 

The other way around however, when I send a 0x0A which is the line feed character it adds a 0x0D which is the carriage return character. I can understand why it is that way and I can filter that out of my data afterwards. (Just to understand all my problems) 

 

The real problem is when I try to send bytes like (0x9F, 0x9E, 0x91- 0x9C, ...) there comes something completely different. For example 0x9F arrives as 0x78 but for 0x78 it also arrives 0x78. 

I can see what I send on SignalTap and I ran different tests, no timing issues. So i think its something nios2-terminal or the Ip core does. 

 

Is there any alternative to nios2-terminal where I don't have all this trouble or does anyone know what I'm doing wrong, except from not using it how its supposed to be used? 

 

Ps: I'm not using NiosII (lack of memory in my project), I access the IP core over the AVALON port, also not how its supposed to be 

So why do I use JTAG UART at all? I'm seriously asking that myself. I thought it would be nice not to need a UART to USB adapter attached to my board and that it would be easy. 

I'm working with the DE10-Lite devBoard with MAX10-10M50DAF484C7G FPGA and my PC is running on WIN10 (64bit) 

 

I would be soooo happy if anyone could help me, 

Thanks
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4 Replies
Altera_Forum
Honored Contributor I
61 Views

Just to have said, for generaly communciation JTAG Master is probably a more straight forward mechanism. but you may have other reasons to not use it.

Altera_Forum
Honored Contributor I
61 Views

@asi_ka: thanks for your reply, 

JTAG Master (JTAG to Avalon Master Bridge) would be an alternative IP to JTAG UART, right? 

But is there a different way to comunicate with then with JTAG UART? 

 

Actually, I didn't have reasons not to use JTAG Master. But I started this project with the idea to use UART as comunication port and then I read about JTAG UART, so I wouldn't have to use a USB to UART adapter.
Altera_Forum
Honored Contributor I
61 Views

If you don't use a Nios then I think it would be easier for you to use the JTAG to Avalon Master IP. Then instead of going through the nios2-terminal, you can write a script in System Console that can directly write to your registers on the Avalon bus.

Altera_Forum
Honored Contributor I
61 Views

Thanks alot for the answers,  

 

As i dont have much time left for my thesis and the comunication interface will be changed anyway later, I found a temporaty solution to validate my output. 

I just record the data with SignalTap and export it to a .csv file. 

 

The next time I have to face that problem I know what I will use. 

 

Thank you
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