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LPDDR2 IP woes

Mikexx
New Contributor I
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I am using the Quartus Lite application from 17.1 to 22.1, all varieties have been tested.

In essence I am porting a design that was tested on a:

  Terasic Technologies Cyclone V GX Starter Kit 

On this I can see functionality and the LPDDR2 works, plus I can use:]#

  Tools -> System Debugging Tools -> External Memory Interface Toolkit

and can see successful calibration.

 

This has been ported over to a bespoke board, and the design fits. The correct pins assigned to the LPDDR2 memory and the CPU_RESET_n assigned to a pin with a pull-up. 50MHz clock is used. There is some confidence that the FPGA is working.

 

What I would like to do is to test the LPDDR2 interface using External Memory Interface Toolkit. However, while I can initialise connections, when I "Link Project to Device" I get an error consistent with all versions of Quartus, except 22.1 where I now get a NIOS error if I run the MegaWizard Plug-in Manager.

The common error line is:

  Internal Error: Sub-system: EMITT, File: /quartus/sld/emitt/emitt_hardware_driver_impl.cpp, Line: 1019

and this precedes a following call stack.

 

I have tried all sorts of variations and conscious that LPDDR2s are probably old hat, but this is all I have to go by.

 

Can anyone help and tell me where I'm going wrong?

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Mikexx
New Contributor I
666 Views

I have used signal-tap to investigate some of the logic levels:

global_reset_n = 1

soft_reset = 1

pll_ref_clk is running at 50MHz

afi_clk is running and is the sampling clock

 

The differences are that:

local_init_done = 0

local_cal_fail = 0

local_cal_success = 0

 

The 3 signals above suggest the calibration hasn't started.

 

Anyone have any ideas on how I can move forward would be greatly appreciated.

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AdzimZM_Intel
Employee
616 Views

Hi Mike,


Are you using an example design generated from Quartus software?


Can you provide some snapshots of the EMIF IP setting as well?


Thanks,

Adzim


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Mikexx
New Contributor I
600 Views

Many thanks for your reply.

This is a bespoke design using a Terasic design involving the HDMI interface. This is based on the 5CGXFC5C6F27C7N. The design has been ported with minimal changes apart from pins in the ".qsf" file.

 

I hope the following helps. They are the same settings for both target devices.

 

1 PHY Settings.png2 Memory Parameters.png3 Memory Timing.png4 Board Settings.png5 Controller Settings.png6 Diagnostics.png

 

 

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AdzimZM_Intel
Employee
585 Views

Hi Mike,


Thanks for the update.

I just want to clarify your problem.

You can use the EMIF Toolkit if you are using Cyclone V GX Starter Kit but you can't use if you are using your own custom board?


Can you provide the error that you are facing when linking the project to device?


In the LPDDR2 IP, are you already configure the Board Settings according to your own custom board?


Do you see any timing violation in the design?


Here is the link for LPDDR2 example design that you can refer to. There also a video that provides some explanation about the example design. https://community.intel.com/t5/FPGA-Wiki/TerASIC-LPDDR2-Example/ta-p/735535


Thanks,

Adzim


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Mikexx
New Contributor I
566 Views

I see, so what you are saying is that I cannot use the LPDDR2 SDRAM Controller IP?

 

I'm not getting as far as a working design. The issue is over using Intel IP Megafunction and trying to get the External Memory Interface Toolkit to work without crashing Quartus.

 

Yes, I have checked and double checked the pins are set correctly in the qsf file, device etc.  The error is in my first post?

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AdzimZM_Intel
Employee
553 Views

Hi Mike,


"I see, so what you are saying is that I cannot use the LPDDR2 SDRAM Controller IP?"

  • No. You can use the IP.


"I'm not getting as far as a working design. The issue is over using Intel IP Megafunction and trying to get the External Memory Interface Toolkit to work without crashing Quartus."

  • Yes I understand that. But which board that you are successfully configured with Toolkit? The Cyclone V GX Starter Kit?


"Yes, I have checked and double checked the pins are set correctly in the qsf file, device etc. The error is in my first post?"

  • So you are seeing an Internal Error when Linking the project to device? If yes, can you provide the error details as well?


Can you test with the example design generated from the Quartus?


Regards,

Adzim



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AdzimZM_Intel
Employee
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As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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