FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Licensed IP & LogicLock or Design Partitions?

Honored Contributor II

We've purchased some 3rd Party IP that we are incorporating into our design. This IP requires a license that is keyed to one particular machine. Other machines on our network have the Altera Quartus license but not the one for this IP. What would be the best approach to allow the other machines to build our full design without having to worry about the IP license? 


I understand that LogicLock does physical placement of regions and Design Partitions performs logical separation. Are either of these suited to 'lock down' the IP compilation so that we don't have to recompile and thus run into licensing issues? Are there different approaches that would be more appropriate (aside from purchasing more 3rd Party IP licenses which really doesn't make too much financial sense.) 



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Honored Contributor II

your best bet is to get a floating license which would allow anyone on the network to compile using the IP. as far as i know, even exported netlists such as .qxp files contain licensing information 


you may be working against the 3rd party or Altera license agreement, so you may ask the vendor what they recommend in your situation 


another solution may be setting up the machine with the fixed license for batch compiles where your users can submit jobs to the machine, but this will take some up front work