FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5982 Discussions

avalon streaming data flow

Altera_Forum
Honored Contributor II
794 Views

Hi 

 

I have cyclone II device, dsp builder and quartus II v6.0. 

I am working on video and image processing project. 

I have read the video and image processing suite v10.0, but still there is not a clear picture in my mind about how the data flow in fpga(in my case cyclone II). 

 

Lets say if my YCbCr video resolution is 640x480, data flow in 2 color spaces, 4:2:2. 

then in the fpga 1st packet will be control packet then the actual data packets will follow that.  

But the question is how many control packets will move 1st? 

and after how much data packets control packets again start moving? 

 

If any body have clear understanding please let me know 

Thank You
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
78 Views

the number of control packets is not defined 

 

most cores append their control packet behind after control packets they receive. the downstream cores are then supposed to respond only to the last control packet received. there are some exceptions, for example the Frame Buffer "processes and discards" incoming control packets
Reply