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Honored Contributor I

avalon streaming data flow



I have cyclone II device, dsp builder and quartus II v6.0. 

I am working on video and image processing project. 

I have read the video and image processing suite v10.0, but still there is not a clear picture in my mind about how the data flow in fpga(in my case cyclone II). 


Lets say if my YCbCr video resolution is 640x480, data flow in 2 color spaces, 4:2:2. 

then in the fpga 1st packet will be control packet then the actual data packets will follow that.  

But the question is how many control packets will move 1st? 

and after how much data packets control packets again start moving? 


If any body have clear understanding please let me know 

Thank You
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Honored Contributor I

the number of control packets is not defined 


most cores append their control packet behind after control packets they receive. the downstream cores are then supposed to respond only to the last control packet received. there are some exceptions, for example the Frame Buffer "processes and discards" incoming control packets