We are using Altera's external memory controller to interface on Stratix with DDR3. The controller on stratix interfaces with Altera PHY IP on one end (which in turn interfaces with DDR3 ) and our driver/user logic on the other end .The driver is a modified version of the example driver that altera Avalon controller and ALTMEMPHY comes with. During normal read/write operations, the driver receives read/write requests from our software and it starts generating addresses to DDR3 attached to stratix. Driver forwards these addresses (row and column addresses) along with read request and burst size to the controller. The controller in turn stores the read /write commands in its command fifo and forwards them to DDR3 and issues local_ready indicating that it is ready for transfer. Local_ready (or waitrequest_n) must be used to throttle reads and writes to the memory controller port. Without local ready, DDR3 will not be in a position to process the request. Problem: Every once in a while, during read access, the command fifo in the controller fills up and it de asserts 'local ready' signal indicating that it is busy and thus the driver/user logic must wait. The issue with the local_ready signal is it permanently goes low preventing any further commands from being accepted by the controller, effectively resulting in the controller being "locked up". So we are stuck in the state machine of the driver. When it locks up, the Stratix stops sending data and software interface issues a retry. But since the state machine on stratix is in limbo, there is no response to retry from stratix. I researched Altera's documents and forums and found out that this is a known issue and has been documented for both read and writes. There have been number of people on Altera forum who have run in to the same problem using this IP. However, none of them have reported any fix for this issue. Can you please assist and help us to get an appropriate solution for this issue?
Hello, In the past year did anyone by chance get to the bottom of this? If so, will you please help me to uderstand what you did to get around this "Known Issue?"Thanks a ton.
I tried to contact altera but didn't get much help. I had to alter my design to not stress cmd fifo too much and though it compromised what we wanted to achieve, it worked. Local ready gets de asserted when cmd fifo fills up, so I reduced the speed of transfer and made sure it doesn't reach there that often. That is the only suggestion I can give you right now.Regards, Sandeep Dattaprasad.