Hi all,I'm using a transceiver in an Arria II GX device with manual lock to reference clock (rx_locktorefclk) / lock to data (rx_locktodata) signals. I'm following the reset sequence for Receiver CDR in Manual Lock Mode. In simulation, my recovered clock always seems to be locked to the reference clock and not to the data -- rx_pll_locked is always asserted after it initially asserts. The time between my FPGA fabric clock and the recovered clock, rx_clkout, is a constant throughout the simulation, and my data drifts with respect to rx_clkout. In the lab on an evaluation board, rx_pll_locked is deasserted after a time, but the errors in my recovered data stream lead me to belive that the clock is not tracking with the data. What are the common reasons why the transceiver fails to lock to the incoming data?
In case you are interested, I figured out that I had to wait until I was receiving data before asserting rx_enapatternalign. I also used rx_clkout for clocking in and aligning the data. I don't switch to another clock domain until after data is aligned.