FPGA Intellectual Property
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Low Frequency Phase Lock Loop

JFK
Novice
231 Views

Could anyone use a Low Frequency Multiplying Phase Locked Loop IP designed for use in FPGA and CPLDs with these specs:

1.  Instant lock
2.  Small foot print
3.  2ns lock to leading edge
4.  10 bit multiplier value
5.  Clock in frequency = don't care
6.  Clock in frequency around 12MHz
7.  Input sample frequency 10Hz to 1000Hz auto ranging 
8.  Stable
9.  Jitter -2ns
10. Generates LOCKED and OVERFLOW
 
If this is of interest to you please let me know and how would you use it?
 
Thanks,
 
Joe
0 Kudos
4 Replies
Ash_R_Intel
Employee
222 Views

Hi,

There is no such PLL in the Intel FPGA portfolio. Most of the PLLs require a minimum of 5MHz input clock. Lock time varies and a minimum value is not published. The max time to lock is generally 1ms for many of Intel FPGA devices.


Regards




Ash_R_Intel
Employee
202 Views

Thanks for the document. I see that this might be a gap in the industry. May be in future someone will implement the invention proposed in the document.

As of now, there is no solution in Intel FPGAs.

Usually low frequency signals are handled by divider circuits or oversampling them using higher frequency clocks.


Regards


Ash_R_Intel
Employee
190 Views

This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


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