Could anyone use a Low Frequency Multiplying Phase Locked Loop IP designed for use in FPGA and CPLDs with these specs:
- New FPGA IP
There is no such PLL in the Intel FPGA portfolio. Most of the PLLs require a minimum of 5MHz input clock. Lock time varies and a minimum value is not published. The max time to lock is generally 1ms for many of Intel FPGA devices.
Thanks for the document. I see that this might be a gap in the industry. May be in future someone will implement the invention proposed in the document.
As of now, there is no solution in Intel FPGAs.
Usually low frequency signals are handled by divider circuits or oversampling them using higher frequency clocks.
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