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Scaler II IP Core Causing Underflow on Clocked Video Output IP

Smith222122
Beginner
353 Views

Hello there,

 

I am having an issue with my Scaler IP core starving my Clocked Video Output (CVO) IP core and causing underflow. I think the issue stems from the scaler requiring a certain number of input pixels to perform its scaling algorithm before it generates a single scaled output pixel. I am trying to scale a 1920x1080 frame down to 1280x800. My IP sequence looks like this:

 

SDRAM ---> Frame Buffer IP (implemented as Frame Reader to read frames stored in SDRAM) ---> Color Plane Sequencer IP (I need to create two seperate video streams, but the other one can be ignored for this issue) ---> Scaler ---> Clocked Video Output.

 

My clocked video output clock is clocking a video stream in at 100 MHz and the output formatted video is clocked out at 65 MHz.

 

The scaling algorithm I am using is the Bilinear algorithm. This was kind of an arbitrary choice based off the resource usage trade off described in the VIP manual. If there is another algorithm that could be recommended that wouldn't require as many input pixels to scale an output pixel I would certainly give that a try.

 

From there I thought that using a frame buffer with repeating frames checked might solve the problem. I thought while the frame buffer was waiting for a scaled frame it could just continually output the previous frame.. The issue I ran into here was the memory requirements. I already have a frame buffer reading the original frame 1920x1080 frame from SDRAM. By adding another frame buffer I am really taxing my SDRAM since the frame buffer has to read and write into SDRAM. Is there any other sort of buffer IP that can take a video stream as input and continually repeat a video stream output until a new frame has been read in?

 

In general, are there any other solutions I am not considering?

 

Thank you for any input!

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6 Replies
ZulsyafiqH_Intel
Employee
292 Views

Hi Smith,


Good Day.

May I clarify the actual video format first? Based on the EIA/CEA-861 standard.


Thank you.


Best Regards,

ZulsyafiqH_Intel


Smith222122
Beginner
286 Views

Hi there,

 

The video format is RGB, 8 bits per color. 

 

Let me know what other information you need!

 

Thanks

vgs
Beginner
270 Views

Hello,

 

At a quick glance you may be trying to do something that isn't possible:

(1920*1080)/(1280*800) = 2

and

100/65 < 2

Assuming your scaler gets one pixel per clock cycle on the input side, the rate at the output will be one pixel every two clock cycles on average. I am not sure how the blanking would affect the numbers but the video path probably needs to be clocked faster.

 

ZulsyafiqH_Intel
Employee
236 Views

Hi Smith,


Thank you for your patience.

Yes I agree with Vgs, the rate is about 2 = ((1920x1080)/(1280x800)).

So the output valid signal will be asserted every two cycles.

I'm afraid the Input clock for Scalar II must be more than 124Mhz which is not included v-sync and h-sync.


Thank you.


Best Regards,

ZulsyafiqH_Intel


ZulsyafiqH_Intel
Employee
225 Views

Hi Smith,

 

We do not receive any response for a while from you on the previous reply.

Hence I will close the case.

If you have a new question, feel free to open a new community forum case to get support.

 

Thank you.

 

Best Regards,

ZulsyafiqH_Intel


Smith222122
Beginner
211 Views

Hi there, 

 

Thank you all for replies. You were all correct. Instead of increasing the main clock running at 100 MHz I reduced the clocked video output clock to 45 MHz and that fixed the underflow issue!

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