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Low Latency 100G Ethernet bring-up : read 0xdeadc0de

Renardo18
New Contributor I
375 Views

Hi,

I am trying to replace the 40G Ethernet IP by the 100G in a new FPGA that I just bought (FPGA is stratix 10 : 1SX280HU2F50E1VGAS).

 

The link is not coming up, I am looping back 2 Ethernet ports of the same FPGA.

When I access the Avalon-MM interface, all the registers that I try to read return the value :

0xdeadc0de.

 

I am guessing it is not a register clock issue (as I wouldn't be able to read anything), nor a reset issue (as some statistics counter value would be 0x00000000).

 

Do you have any idea of what could be happening here?

 

Regards

0 Kudos
1 Solution
Deshi_Intel
Moderator
354 Views

HI,


One of the possibility is you are reading the reg from invalid/incorrect memory region.


You may want to check the reg address memory mapping in your design again.


Thanks.


Regards,

dlim


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5 Replies
Deshi_Intel
Moderator
355 Views

HI,


One of the possibility is you are reading the reg from invalid/incorrect memory region.


You may want to check the reg address memory mapping in your design again.


Thanks.


Regards,

dlim


Renardo18
New Contributor I
329 Views

Hi Dlim,

actually I noticed that I had forgotten to enable RS-FEC in the IP, since I enabled it, my design is not able to pass fitter.

Fitter reports "cannot place node [...] for hundreds of lines.

My design is very simple and almost empty (only 10% of FPGA logic is used), it contains :

4 times :

[100G ethernet IPs] + logic to answer to an ARP or ICMP request (ton answer PING).

 

I am guessing the design is not constrained enough, I have generated the low latency 100g ethernet FPGA ip example design, and I got inspired by the .sdc constrain file provided in it. Basically :

 

for { set i 0 } { $i < $x100g_count } { incr i } {
set THIS_RX_RS_CORE_CLK [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|WITH_FEC.fecpll|RXIOPLL_INST.fecrxpll|alt_e100s10ex_iopll_rx_outclk0]
set THIS_RX_RS_CORE_NCK [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|WITH_FEC.fecpll|RXIOPLL_INST.fecrxpll|alt_e100s10ex_iopll_rx_n_cnt_clk]
set THIS_TX_RS_CORE_CLK [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|WITH_FEC.fecpll|TXPLL_IN.TXFPLL_INST.tx_pll_gen.fectxpll|clkdiv_output_div1]
set THIS_RX_CORECLK [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|xcvr|rx_clkout2|ch1]
set THIS_TX_CORECLK [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|xcvr|tx_clkout2|ch1]
set THIS_REF_CLK [get_clocks cg_ref[$i]]

set_clock_groups -exclusive -group $THIS_TX_CORECLK -group $THIS_RX_CORECLK -group $THIS_TX_RS_CORE_CLK -group $THIS_RX_RS_CORE_CLK -group $THIS_RX_RS_CORE_NCK -group $TRS_DIVIDED_OSC_CLK -group $STATUS_CLK -group $REF_CLK

}

 

# set false path from PMA fifo flags' clock to clk_status (ex_100g_inst|ex_100g_inst|alt_s100|csr|eio_flags_csr[*])
for { set i 0 } { $i < $x100g_count } { incr i } {
for {set chNum 0} {$chNum < 4} {incr chNum} {
set RX_CLK [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|xcvr|rx_pcs_x2_clk|ch$chNum]
set TX_CLK [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|xcvr|tx_pcs_x2_clk|ch$chNum]

set_clock_groups -exclusive -group $RX_CLK -group $STATUS_CLK -group $TRS_DIVIDED_OSC_CLK
set_clock_groups -exclusive -group $TX_CLK -group $STATUS_CLK -group $TRS_DIVIDED_OSC_CLK
}
}

 

 

 

Do you see any constraint missing here? 

 

Thanks

aleytu145
Beginner
326 Views

Hi,

 Hopefully, now your problem is solved. Let me know if you need any help yet because i handled the same issue few days ago.

Thanks

Renardo18
New Contributor I
325 Views

Hi Aleytu,

 

no my problem is not solved... Can you let me know how you handled it?

 

Thanks

Renardo18
New Contributor I
191 Views

Hi all, problem is solved.

 

For 0xdeadc0de : I had an error in my addressing register, I was reading a wrong address.

For the placement : I updated to Quartus 20.2

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