We've implement the low latency 100GE core with CAUI-4 in an Arria10 GT. About every 30 minutes the 100GE switch reports a burst of errors and takes the interface down. We suspect that there is an issue with lane to lane skew possibly due to clock drift causing a loss of channel bonding. The ATX PLL's (GT mode) are using the same reference clock but it is not from the closest refclk input. Could there be an issue? I'm assuming the transmit data is being launched to the GT PHY devices at the same time with locked clocks or a single clock.
Any help is appreciated.