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Low latency 100GE core with CAUI-4 sends bit errors at regular intervals to switch

SKinz
Novice
438 Views

We've implement the low latency 100GE core with CAUI-4 in an Arria10 GT. About every 30 minutes the 100GE switch reports a burst of errors and takes the interface down. We suspect that there is an issue with lane to lane skew possibly due to clock drift causing a loss of channel bonding. The ATX PLL's (GT mode) are using the same reference clock but it is not from the closest refclk input. Could there be an issue? I'm assuming the transmit data is being launched to the GT PHY devices at the same time with locked clocks or a single clock.

 

Any help is appreciated.

Thanks

Skip

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1 Reply
SengKok_L_Intel
Moderator
124 Views
Hi Skip, when the interface is down, does reset of the 100G IP can bring the link up again, or it can recover without reset ? Does the same problem occur if you perform an external loopback test (FPGA TX -> Cable -> FPGA RX)? Any frame error (from statistic counter) observed before the link down? Is the refclk located at the same side with the transceiver bank? Regards -SK Lim
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