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Honored Contributor I
1,483 Views

MPEG Transport stream over IP?

hi 

 

i search a IP Core that can convert the MPEG transportstream (ASI (e.g with the ASI-Megafunction) or SPI) to ethernet. 

 

i find only the "10G RTP Video over IP" from Macnica. This is only für the stratix FPGA. 

 

exist any core for cyclone III or cyclone IV? 

 

Thanks :)
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Honored Contributor I
51 Views

Hey Nomex,  

 

I am searching for the same IP, did u find any IP ?  

 

Thanks ;) 

Jalayan
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Honored Contributor I
51 Views

I've made that by myself easily. I've actually made an IP streamer with two ASI streams streamed to different IPs or ports. 

You should pack up to 7 MPEG-TS packets together, put UDP header, put IP and MAC headers -> move it to the TSE core and that's it. You also will need a small round-robin scheduler if you want to handle the incoming packets by LwIP and Nios. 

All of this fitted to Cyclone III, both streams worked at 200Mbps, so 400Mbps over Gbit link overall.
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Honored Contributor I
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Hi Socrates, 

 

I'm very interested in trasmission of a TS over IP network, but I'm starting now thinking about the problem. Could you explain better your solution and share any code?  

Are you encapsulate the 188-bytes of each TS directly into an UDP (example multicast???) and are you able to receive on a laptop connected to the network using for example VLC? 

It's also very interesting the possibility to add LwIP and Nios could you provide more details? 

 

Thanks in advance
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Honored Contributor I
51 Views

There is a reference design from altera (click) (https://www.altera.com/products/reference-designs/all-reference-designs/broadcast/ref-video.html

Its application note can also be found here (click) (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0ahukewi12qqg6ltrahxhqxokhz1rbw0...

This reference design is too large (due to Nios) and lacks jitter control. If you want to design from scratch, it is not difficult. 

You should be well informed about MPEG-TS, RTP, UDP, and Gigabit Ethernet interface. 

You need a DDR controller and DDR memory if you want low jitter output, otherwise you can do it using FIFOs inside FPGA.
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Honored Contributor I
51 Views

If you just have a single IP stream over a dedicated link, jitter shouldn't be much of a problem. What is the goal with the stream.. just to view it or something more involved?

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Honored Contributor I
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Thanks guys for your replies. 

 

@msj the second link does not work. 

 

The idea is: take some TS directly from a front-end and wrap intoa UDP stream, then watch using VLC on my pc or using raspberry pi connected to the TV thru HDMI 

 

Maybe it's a silly question: does the 188-byte packet of TS became the RTP payload?  

 

Is there any low cost board with an altera fpga and ethernet adapter? I have already bought a Terasic De0 Nano (cyclone IV) but it has not theethernet adapter. Could you advice anything?
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Honored Contributor I
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The link corrected. 

For VLC or even TV play, jitter is not a problem. It could be a disaster if you want to broadcast it using DVB modulators. So forget about jitter in your project. 

The 188-byte TS becomes the RTP payload, but there are other fields that should be inserted, like Time Stamp, Sequence Number, etc. 

Study the SMPTE-2022-2 standard for more detail.
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