MSGDMA Read and Write Masters

[NGord]

Hi,

The MSGDMA is deliberately designed to be modular.
As such , if I wanted to utilise the Read and Write Master IP without the Dispatcher, there is no published specification for the Command and Response Ports.
Why is that? Are we forced to use the Dispatcher with a Host port or can we use the FPGA fabric to interface with the Command and Response Ports directly assuming there is a specifcation for them somewhere?

[Jeet14]

Hi

Please help to share more details on this.

1. Device/development kit details used?
2. are you using any GHRD or GSRD for this?
3. Is this about the PCIe, MSGDMA and the PC Host driver?

Regards

Tiwari

[NGord]

1. Device/development kit details used? -MAX 10: 10M40DAF256I6G
2. are you using any GHRD or GSRD for this? -No
3. Is this about the PCIe, MSGDMA and the PC Host driver? -Its about the Command and Response Ports of the below.
   There is zero information on them apart from telling me to use them with the Dispatcher which I dont want to do.
   I want to add my own Controller. So details please!
   

[Jeet14]

Hi,

Please refer the example design for MSGDMA for Arria 10. This is having NIOS II, MSGMDA.

https://community.intel.com/t5/FPGA-Wiki/MSGDMA-design-example/ta-p/735335

You can try porting above reference design to MAX 10.

Regards

Tiwari

[Jeet14]

Hi,

Let me know if you have any query on this matter.

Regards

Tiwari

[Jeet14]

Hi,

I believe your inquiry has been answered. With that, I now transition this thread to community support. 

Thank you.

Best regards,

Tiwari

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[NGord]

I dont believe this matter is closed.
The example you gave doesnt show individual Read and Write Masters, and makes no mention of them.