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MSGDMA and Hard Memory Controller Interface


There is an issue with our MSGDMA and Hard Memory Controller interface. We are using the MSGDMA to read from DDR Memory via the Hard Memory Controller. 

In the attached snapshot from Signal Tap, you will see that after the first 8 128bit word transfers, the MSGDMA readdata shows zeros. We expect there to be 64 transfers as shown by the burstcount of 64.

We have verified that the first 8 words match data that is in DDR but the zeros do not. There is valid data in the DDR that should be being read out. Additionally, we noticed that the Hard Memory Controller is asserting both the waitrequest and readdatavalid lines which does not make a lot of sense. 

See attachment1


We've made a discovery. We added the Video Frame Buffer(VFB) write master going to the Hard Memory Controller (HMC) and saw that the VFB is writing to an address that the MSGDMA is trying to read from. 

You can see this behavior below. Also for reference, we disabled burst enable on the MSGDMA for this run.

See attachment2


This race condition is likely causing our "missing data". We were assuming that the entire subframe had been written to memory by the time the MSGDMA descriptor telling it to read the subframe from memory was issued.

In our application, for each incoming frame, we check and clear the Available Bit before sending a subframe ready signal that tells our other user logic to issue a descriptor.

However, it would appear that the frame being "written and available to read" does not mean it is done writing the frame, but rather it has started writing the frame.

Please let us know the correct way to interpret this Available Bit and or a way to know that the VFB has completed writing the full frame to memory.

See attachment3 

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Hi EDing,


May I know what are the setting used in the Frame Buffer? Can you share the setting applied if you don't mind?


And do u turn on Frame Writer mode?


If you turn off the Frame Writer mode in your setting, then Bit 31 is invalid but you can perform both read and write to DDR IP . If this setting is turn on , then the Available bit is valid but you can only perform read to DDR IP.


What I can see here is you want to perform read and write to DDR, by right this Frame Writer mode need to turn off .












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