I have downloaded an MSIx example design from the link -"https://www.intel.com/content/dam/altera-www/global/en_US/uploads/c/cc/Msix_avmm_ref_design.zip".
There is top level file "pcie_irq.v" which has several interfaces and I understood the significance of the Interfaces except "Slave PBA local Interface". Please correct me if I am wrong.
"Slave Interface": Through this interface host cpu will fill the MSIx table only and read the PBA table
"IRQ interface": Through this interface interrupts will be recieved from the four irq sources which can generate interrupts when on requested by host cpu through BAR4
"Master Interface": Through this interface an Interrupt will be generated by sending data to particular address specified by the host in the MSIx table during the enumeration
And please let me know the significance of the "Slave PBA local Interface"