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I have searched and searched, but unable to find a 'reference' document on any of the OpenCL components, such as:
- ACL global Clk Signal
- ACL DMA to PCIe Bridge
- ACL SW Reset
And others listed under "ACL Internal Components"
Also, there are the OpenBSP Components:
- OpenCL A10 Kernel Clock Generator
- OpenCL Kernel Clock Generator
- OpenCL Kernel Clock Generator - no Dynamic Reconfig
I also have examples in Platform Designer that include "OpenCL Kernel Interface" -- which is very important, but not documented *ANYHERE* that I can find.
I'm convinced there is documentation "somewhere", but finding it on the *MASSIVE* Intel site is near impossible. Can someone point me in the right direction??
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Hi
can you please clarify , for which platform you are seeking the information. Is it for an Arria10 , Stratix10 or a PAC card.
Please let us know.
Thanks and Regards
Anil
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This is for the Cyclone V. I have two boards really, a Terasic De10-Nano, and a CriticalLink Mitysom Cyclone V.
I have discovered that some of the parts I see are in the `intelFPGA/19.1/hld/ip/board/iface` directory. Some of these are the acl_kernel_clk.qsys, acl_kernel_interface_soc.qsys, etc.
Within these, the sub-systems use some of the standard IP, such as a Clock Bridge, Reset Bridge, etc, but some also use "ACL internal components", and I cannot find any documentation on those. Examples of these are:
- ACL Bank Splitter w. Reorder
- ACL Burst Boundary Splitter
- ACL irq ena
- ACL No Reset
And others.
These show up in "Platform Designer" under the IP Catalog, under "ACL Internal Components" -- but I'm not sure how that directory got added to my project, or where the information on it is.
I find that the actual documentation for the OpenCL implementation, form a Board Support Package, is really terrible -- I've spent weeks, several months even, trying to understand this stuff, and it's been very frustrating and difficult to navigate. I'd really appreciate a bit more detail on information about implementing a Board Support Package with OpenCL.
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Hi
You can get information about the components by clicking on the items in the platform designer.
The following links can give more insight also about BSP and customizing your platform.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/ug_aocl_custom_platform_toolkit.pdf
There are some information about the components which is in public domain , like the one below for S10.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/ug-aocl-s10pciedk-platform.pdf
If you have a specific use case which requires an internal information of the components , please let us know .
Thank and Regards
Anil

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