- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello.
I am using a Cyclone V PCIe Hard IP on a 5CGXFC3B6U19I7. I have been struggling to get the PCIe to reliably come out of reset. The design passes timing and I believe that it is setup correctly. This issue appears to occur most often when it is cold (approx. 10°C).
I can see that the IP core is simply not resetting properly as with a SignalTap analysis, it is clear that the pld_clk_inuse signal is not asserted, despite the fact that the PERST signal has deasserted. Strangely, however, the nreset_status signal appears that it is deasserted. This seems to indicate that the reset is not happening or the IP core is not initialising.
I have attached a snapshot of the HIP_status_ext signals from signaltap.
Please help.
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Is it possible to send the same project just want to check the reset is connected properly .
And also want to know , the design is working as expected in other temperature setting
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Rahul
I managed to send you a private message. Please check that for the information that you requested.
Regards,
Stuart
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I will get back to you
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Communication is taken in to private message
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page