Cyclone V PCIe Hard IP is not initialising/resetting

[SSmit7]

Hello.

I am using a Cyclone V PCIe Hard IP on a 5CGXFC3B6U19I7. I have been struggling to get the PCIe to reliably come out of reset. The design passes timing and I believe that it is setup correctly. This issue appears to occur most often when it is cold (approx. 10°C).

I can see that the IP core is simply not resetting properly as with a SignalTap analysis, it is clear that the pld_clk_inuse signal is not asserted, despite the fact that the PERST signal has deasserted. Strangely, however, the nreset_status signal appears that it is deasserted. This seems to indicate that the reset is not happening or the IP core is not initialising.

I have attached a snapshot of the HIP_status_ext signals from signaltap.

Please help.

[Rahul_S_Intel1]

Hi,

Is it possible to send the same project just want to check the reset is connected properly .

And also want to know , the design is working as expected in other temperature setting

[SSmit7]

Hello Rahul I tried to send you a private message, but it failed owing to the large file size. How can I send you a message with the necessary information? Regards Stuart

[SSmit7]

Hi Rahul

I managed to send you a private message. Please check that for the information that you requested.

Regards,

Stuart

[Rahul_S_Intel1]

Hi,

I will get back to you

[Rahul_S_Intel1]

Hi,

Communication is taken in to private message