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MSI-X Interrupts not aligning to 32-bit boundary

Altera_Forum
Honored Contributor II
785 Views

We are having a problem issuing MSI-X interrupts. We are running a Cyclone V HIP PCIE 1x1 on a 64-bit Linux machine in 64-bit data/64-bit addressing mode. I generate the interrupt to the address specified by the system at the slave interface but when I capture the TLP the destination address is being aligned to a 64-boundary even though the system has given me a 32-boundary address. Anyone know why this could be happening?

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Altera_Forum
Honored Contributor II
107 Views

Maybe because PCIe is basically a 64bit interface? 

Certainly a normal 32bit data write is a 64bit transfer with only 4 (of 8) byte enables asserted.
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