FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

MSI generation in PCIe

Sudhirkv1
Beginner
733 Views

Hi,

We have been trying to generate MSI interrupt through the RXM_irq input port by making it external on the platform designer. We do not have a DMA engine connected to PCIe, but if look at the testbench system created, specifically at altpcietb_bfm_driver_avmm.v, The MSI interrupt generation is only in dma_mem_test and not on the target_mem_test. We have connected bar0 to the CRA port in our design and hence we are using target_mem_test_lite in this driver BFM. I have modified the testcase similar for this at target_mem_test_lite from dma_mem_test for MSI interrupt generation (Please refer to the attached file).

After writing register 0x50 to 0x00010000 (Bit 16 is used for MSI enable) (cra_msi_enable.png), When we try to read Interrupt Status Register (0x0040), the value we read is 0x0 (Refer to attached snapshot (cra_read_rxm_irq.png).

Could anyone please guide us on how to properly generate MSI interrupts with these configurations.

We are also attaching the Archived Quartus project for reference.

Regards,

Sudhansh Garg

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5 Replies
Rahul_S_Intel1
Employee
702 Views

Hi ,

 As primary information, is the MSI enable bit is set 

Sudhirkv
Novice
696 Views

Hi Rahul,

 

Thanks for your time.

Yes we have set the msi_enable bit set to 1. 

We have also attached the testbench file in the earlier post. 

 

Regards,

Sudhir

Rahul_S_Intel1
Employee
666 Views

Can you please help to give your number in private message , so that I can call you.

 

Rahul_S_Intel1
Employee
603 Views

May I kindly close the issue, as the issue is open for quite a long time.  Kindly requesting to open a new thread if the issue is still open  

Rahul_S_Intel1
Employee
553 Views

Kindly let me know if you have additional questions 

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