I have a MAX 10 design (part: 10M08SAM15317G) in which I'm attempting to use the MAX 10 ADC Hard IP Block to capture signals on the dedicated Analog Input (Pin ANAIN) while preserving the the dual purpose analog inputs (ADCIN[1..8]) for digital IO.
I have configured the MAX 10 ADC Hard IP Block to only use CH0 (ANAIN) while de-selecting CH1-8 and TSD inputs. However, during placement I still get conflicts on all of the dual purpose analog inputs like so:
Info (176311): Pin lh_data_io is assigned to pin location Pin_G5 (IOPAD_X10_Y21_N21) Info (176311): Pin ~ALTERA_ADC1IN4~ is assigned to pin location Pin_G5 (IOPAD_X10_Y21_N21)
Is it possible to use the MAX 10 ADC Hard IP Block to capture analog signals from ANAIN while preserving the dual purpose analog inputs for digital signals? If so, what configuration is required to do this?
OK, that is definitive.
Can you point me to the documentation where this is specified? If not, I would suggest that the documentation is updated to make this clear if the ADC Hard block is used, all digital IO, including the MUXed, non-dedicated inputs are not available for digital IO.
Thank you for your help!