- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I am working on a Cyclone10LP120 and a MT25QL512 using the Generic Serial Flash Interface.
At the moment, i'm trying to execute basic features such as sector R/W which works fine. However I am not able to lock sector by sector (64KB) since I still can modify data inside these sectors. I found an example provided by Intel with low level instruction such as IORD or IOWR. In the documentation, it is mentioned there are HAL drivers available but there is none when generating bsp files.
My questions are :
- Do I need to switch to a newer version of Quartus to enable GSFI HAL drivers?
- (or) Is there someone who knows which low level instructions I need to perform to lock individual sectors?
In the MT25Q 512 datasheet, I see it's possible to lock 64KB sectors by setting bits Top/Bottom, BP[3:0].
I'm performing the followings :
/* GENERIC SERIAL FLASH INTERFACE */
#define GSFI_CTRL_REG 0x0
#define GSFI_SPI_BAUDRATE_REG 0x1
#define GSFI_CS_DELAY_REG 0x2
#define GSFI_RD_CAPTURING_REG 0x3
#define GSFI_OP_PROTOCOL_SETTINGS_REG 0x4
#define GSFI_RD_INST_REG 0x5
#define GSFI_WR_INST_REG 0x6
#define GSFI_CMD_SETTINGS_REG 0x7 // refer to page 37 of MICRON datasheet for opcodes
#define GSFI_CMD_CTRL_REG 0x8
#define GSFI_CMD_ADDR_REG 0x9
#define GSFI_CMD_WR_DATA_0_REG 0xA
#define GSFI_CMD_WR_DATA_1_REG 0xB
#define GSFI_CMD_RD_DATA_0_REG 0xC
#define GSFI_CMD_RD_DATA_1_REG 0xD
/* MT25QL512 */
#define MASK_WRITE_IN_PROGRESS 0x00000001 //set mask to check Write in Progress (WIP) bit to determine device busy or ready
#define ALL_SECTOR_UNPROTECTED 0x00000083 // set mask to check bit 6,4:2 of status register
#define ALL_SECTOR_PROTECTED 0x0000007C //set BP3-0 and Top-Bottom bit in status register to protect all sectors
#define BOOT_SECTOR_PROTECTED 0x00000068 //set BP = 1010 and TP = 1
#define APP_SECTOR_PROTECTED 0x00000048 //set BP = 1010 and TP = 0
#define MASK_ERASE_ERROR 0x00000020 //set mask to check erase error bit in flag status register
#define MASK_WRITE_ENABLE_LATCH 0x00000002 //set mask to check write enable latch
void boot_sector_protect(){
PRINTF("Now performing BOOT sector protection...\n");
write_enable();
if ((read_status_register() & MASK_WRITE_ENABLE_LATCH) != MASK_WRITE_ENABLE_LATCH) { //check if write enable latch is set
printf("Sector erase cannot be executed as write enable latch do not set\n");
return NOK;
}
IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE, GSFI_CMD_SETTINGS_REG, 0x00001001);// OPCODE = WRITE STATUS REGISTER
IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE, GSFI_CMD_WR_DATA_0_REG, BOOT_SECTOR_PROTECTED); // GSFI FLASH COMMAND REG + See status register of MT25 (p.20). 0x68 => TP : 1'b1, BP = 4'b1010 -> 511:0 = protected
IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE, GSFI_CMD_CTRL_REG, 0x1); // START OPERATION
usleep(1000000);
while (read_status_register() & MASK_WRITE_IN_PROGRESS == MASK_WRITE_IN_PROGRESS){
usleep(1000);
}
PRINTF("Status Register: %08x\n",read_status_register());
if ((read_status_register() & BOOT_SECTOR_PROTECTED)!= BOOT_SECTOR_PROTECTED) {
PRINTF("BOOT sector protection failed due to error in setting status register\n");
PRINTF("Status Register: %08x\n",read_status_register());
return NOK;
}
PRINTF("BOOT sectors successfully protected\n");
return OK;
}
Thank you for your answers
John
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I am looking into this issue, this may take a few days to a week.
Thanks for your patience.
Have you previously use other HAL drivers before?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Dear EBERLAZARE,
Thank you for your reply but I think I found the solution or I rather understood how the GSFI works.
In fact, when one wants to erase or lock sectors in FLASH, you have to insert CSR commands with the TRUE address range of the MT25 and this is pretty normal.
However, when one wants to read/write data using AVMM interface inside MT25, it is necessary to divide addresses by 4 (shift right 2).
The way Qsys displays the AVMM address range is a bit misleading to be honest because it shows the MT25 address range which is
0x00000000 -> 0x03FFFFFF.
For example, if you read address 0x02000000, you have a copy of what is written at 0x00000000. That's why I thought there was a problem.
To answer your question "Have you previously use other HAL drivers before?", there is no HAL drivers for the GSFI in quartus prime 20.1. Instead, Intel provides a very low level example to use the GSFI with IORD & IOWR. In this example, it only shows how to r/w at address 0x00000000.
Thank you EBERLAZARE
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Thanks for the update and feedback.
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page