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Error (10773): Verilog HDL error SystemVerilog extensions

assn1
Novice
3,072 Views

 

Well, there's a problem.

 

Error (10773): Verilog HDL error at timer_control.v(5): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions


This warning came up, so I did System Verilog extensions when I set up the module... Probably.
But this error still pops up. Is there a solution?

 

<code>

module timer_control(RESET, CLK, SW, DATA);

input RESET, CLK;
input [2:0] SW;
output [7:0] DATA [31:0];       //<--  This is an error code!

integer count;

reg [6:0] min, sec, m_sec;
reg [6:0] rec_min, rec_sec, rec_m_sec;

reg start, lab;

always @ (posedge CLK) begin
if(~RESET) begin
count = 0;
end
else if(start) begin
if(count == 10) begin
count = 0;
m_sec = m_sec + 1;
end
else begin
count = count + 1;
end
if(m_sec == 100) begin
m_sec = 0;
sec = sec + 1;
end
if(sec == 60) begin
sec = 0;
min = min + 1;
end
if(min == 60) begin
min = 0;
end
end

end


always @ (*) begin
if(~RESET) begin
start = 0;
rec_min = 0;
rec_sec = 0;
rec_m_sec = 0;
lab = 0;
end

if(SW[2])
start = 1;

if(SW[1])
start = 0;

if(SW[0]) begin
rec_min = min;
rec_sec = sec;
rec_m_sec = m_sec;
lab = 1;
end
end

binary_to_digit min_control (min, MIN_FRONT, MIN_END);
binary_to_digit sec_control (sec, SEC_FRONT, SEC_END);
binary_to_digit s_sec_control(m_sec, HOUR_FRONT, HOUR_END);

endmodule

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3 Replies
sstrell
Honored Contributor III
3,053 Views

You're putting a 2D array on an output instead of an internal RAM (which is what I'm guessing you are trying to implement).  Shouldn't this be not in the port list like this:

reg [7:0] DATA [31:0];

Found a super old post that might help as well:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/SystemVerilog-Extensions-Error/m-p/171487#M42427%3Fwapkw=quartus%20error%2010773

 

ak6dn
Valued Contributor III
3,036 Views

(1) The output port DATA is never referenced in your module code. So is it really needed?

(2) You can't use multidimensional arrays in ports in verilog. Use DATA[255:0] instead and manually assign bit fields.

(3) Use the <CODE> block feature of this forum. It makes your code MUCH easier to read and understand.

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ShengN_Intel
Employee
3,009 Views

Seems like the issue addressed had been resolved. I'll now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts.


Thank you.


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