I try to write data to the internal flash, noticed that somehow the waitrequest signal is asserted for one clock cycle only. The clock is 25mhz. I noticed it through the signaltap..
Typically, waitrequest signal assert when the On-Chip Flash IP is busy during read or write operation. However, for your case I’m not really sure why waitrequest only assert for one clock cycle. Could you please attach your signal screenshot here?
Do you choose parallel or serial option for Data Interface in On-Chip Flash IP parameter?
And one more thing, which MAX 10 family device you used for your design? (10M02 or 10M50 or ?)
Looking forward for your reply.
this is what i'm see in the signaltap.
the flash is configured parallel and im using the 10M50DAF484 device (currently using the altera eval board).
my design is a qsys design, avmm pipeline bridge which is the master of the onchip flash (data and csr), dual boot and sysid slaves. the bridge is exported outside of the qsys design to my custom controller which translates uart commands to the avalon bus.
anyway i see that when i want to write data to the flash instead of sampling the waitrequest port for writing the next data, i need to wait in the host until writing the next data. why do you think the waitrequest signal dont acts as it supposed to be? as i understood from the ug_m10_ufm document, the waitrequest should be asserted for maximum 0.5 msec.
im working with quartus 15.1.0, maybe the ip is not last updated? if so, how do i update the ip?
so i checked the issue and noticed that in signal tap if i check the ports of the onchip flash (whithin the qsys) directly, i see that the waitrequest asserts for approximately 1.5 usec.
changed the avalon bridge parameter to disable all the pipeline features. and now i see differeent behave of the waitrequest.
but still, isnt it too short time?
another thing i noticed is that if i sample the readdata port of the csr interface of the onchip flash, i can see in live the status of the flash. ive seen that many times the write fail flag of the status register is asserted.
any idea why?