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Maximum Operating frequency: NIOS2 system on Max10

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I have built a NIOS2 based SoC system with most of the IP's used from IP Catalog. The targeted evaluation board for this is the Intel Max10 FPGA Development kit (DK-DEV-10M50-A)o. The system components used to build the system on Platform Designer contain the clock source, NIOS2 CPU, On chip memory, JTAG UART, Timer, WDT, On Chip Flash, ALTPLL and finally a custom component of our designer. This entire system is build on platform designer and attaching a screen shot from the built system. Upon synthesis in Quartus II and timing analysis, the maximum possible frequency achievable is 48MHz as per the timing reports. See the attached detailed timing report. The clock is used from the ALTPLL block. The timing path starts from the NIOS2 CPU and through the interconnect and passes through onchip flash control and eventually ends at the DMA. Is this the maximum achievable frequency for this system? Do you have any recommendations on how can i increase the frequency of operation of this system?

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To optimize the Qsys interconnect, you can refer to this UG https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/qts-qps-5v1.pdf?wapkw=quartus+handbook+18.1+standard, 8-12 Inserting Pipeline Stages to Increase System Frequency & 8-13 Using Bridges. The first method can be easily applied, just changing one setting, and should give some improved Fmax result but it incurs some latency in the transfer.
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