Memory port limits on Stratix V

[Altera_Forum]

I've been trying a few things to get memories with more than two ports but having some difficulty. If I use the megawizard tool, I only get choices of 1 and 2-port rams (under memory compiler). I see some mention of tri-ported rams in the documentation but I don't see a direct way to build them. I am able to infer rams with more than two ports, but there seems to be a limit in size (which I haven't found exactly yet) where the program runs out of memory while trying to compile if the ram is too large. So does anyone know what the story is with three or more ported rams? When inferred, do they just build multiple copies of 1 or 2-ported rams?

[Altera_Forum]

AFAIK the only way to create more than 2-port rams is by using HDL code. 

Do you need all your ports to have read and write access? In that case you can't use the embedded RAM blacks and the synthesizer will infer registers. This will use a lot of memory to compile the design and use a lot of resources on the FPGA if your memory block is big.  If you only have one port with write access then in theory it is possible to implement the function using several dual port blocs in parallel, but I don't think the synthesizer will do that automatically for you. You'll probably have to do it manually in your HDL code.