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Hi, All,
I'm trying to use the On-Chip FIFO Core that comes with Qsys, with a costume module that I've built. My module has an Avalon-MM Master port, and I'm connecting it the the In port of the FIFO. (Single clock, 32 bit wide, no status interface). When generating, I'm getting an error about the Altera_Merlin_Slave_Translator prefix: "Part select direction is opposite from prefix". I checked my Master port, and it's configured roughly like that: avm_writedata: out std_logic_vector(31 downto 0) avm_write: out std_logic I'm stumped...any ideas? Thanks, RanLink Copied
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