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I am trying to simulate my verilog modules in modelsim. When I try to include .v files as headers in my modules, modelsim still tries to compile them and complains that global variables are not allowed. I tried to circumvent this by including an .inc file instead(which seems to work?) and got past the compilation phase. Now when I try to simulate my top level module, I get the following error:
# ** Error: (vsim-3033) C:/Users/abdelfadel/Desktop/xillybus_beta_core_pipelined/verilog/output_fifo.v(74): Instantiation of 'dcfifo_mixed_widths' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /test_wrapper/inst/generate_structure[3]/output_fifo_inst File: C:/Users/abdelfadel/Desktop/xillybus_beta_core_pipelined/verilog/output_fifo.v
# Searched libraries:
# C:/Users/abdelfadel/Desktop/xillybus_beta_core_pipelined/verilog/simulation/modelsim/rtl_work
I am starting modelsim from Quartus by clicking on tools ->run simulation tool -> RTL simulation
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Hi,
Can your try the steps as below:
1)Update Quartus to the latest version and the latest version for each Quartus Prime edition as below:
Quartus Prime Pro 19.2
Quartus Prime Std 18.1
Quartus Prime Lite 18.1
Caution: Must be refer to the device support in each version
You may refer to the link below:
https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html
2) ModelSim simulation in Quartus Prime Std and Web edition by using native link to launch the simulation. The links below show the setup using native link :
https://www.altera.com/support/support-resources/design-examples/design-software/simulation/modelsim/exm-ncsim-native-link.html
https://www.youtube.com/watch?v=PmVVXQchv2c
3) ModelSim simulation in Quartus Prime Pro edition:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20093.pdf
https://www.youtube.com/watch?v=eviC0jP90ZA
Thanks.

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