Hi everyone,I am trying to modify the QSys PCIe reference design (AN431) for a Cyclone IV Starter Kit equivalent. The reference design works on my board after I modified the pin mappings and PLL settings. I get transfer rates of 195MB/s (FPGA->computer) and 120MB/s (computer->FPGA). These speeds are obtained using the Windows program that came with the reference design. Here's my understanding of the system: http://img12.imageshack.us/img12/176/an431.png I am trying to transfer data over PCIe with DMA. To do so, I am moving data into the OCM (on chip memory) and transfering the contents of the OCM via DMA. To do this, the OCM was modified to be a dual port memory. The second port was exported from the Qsys design. Data is constantly being written to the exported port. In essence, I created this system: http://img202.imageshack.us/img202/2865/an431modified.png The problem is DMA transfer now is intermittent and fails on occasion. The smaller the transfer size, the higher the likelihood of success. When it succeeds, the transfer takes place at the full speed that it did prior to modification. So, my question is, why is it failing and what can I do to fix this? My first hypothesis is that perhaps its a read during write that is causing the failure. However, this does not seem plausible because there is no feedback from the OCM which can cause the Avalon bus to stall. The signals coming out of each slave port of the OCM are:
address chipselect clken readdata write writedata byteenableI don't see any signals which could cause the system to wait. I wouldn't even know which signals to probe if I were to use SignalTap. Does anyone have any suggestions?
I'm not sure about the size that you are sending, but in general, if the data size is not aligned to..I think 64bitx16, the DMA won't work correctly.You just need to open the setting of mSGDMA. I think the PCIe interface is 64bit, so you just need to check the burst length. It has to be exact length in that design. If you want to send much smaller data, change the setting of the mSGDMA, so you can send whatever size you want. The other thing I can think of is accessing same address of the OCM? if so, use 2 pgaes of location. For example, page0 start from offset address of 0x0000 - 0x7FFF page1 start from offset address of 0x8000 - 0xFFFF external port uses like page0, page1, page0, page1 whereas PCIe or mSGDMA should read page1, page0, page1, page0 to avoid conflict.
--- Quote Start --- Hi everyone, I am trying to modify the QSys PCIe reference design (AN431) for a Cyclone IV Starter Kit equivalent. The problem is DMA transfer now is intermittent and fails on occasion. The smaller the transfer size, the higher the likelihood of success. When it succeeds, the transfer takes place at the full speed that it did prior to modification. So, my question is, why is it failing and what can I do to fix this? --- Quote End --- Hello, serendipity! Did you find the cause of Your problem?
Yes. It has to do with the software (I think). The software looks for a magic number at the end of the transfer buffer to signal the end of a transfer. The counter was not writing this magic number.I changed the design to write the magic number (32 or 0x32? can't remember, its been a while). The reference software worked and I got the same transfer rates.
Yes! I would have expected an IRQ as well. I think I read the magic number in the source code somewhere, but I don't remember which one. It was as blatent as an if statement in a loop comparing the last element of an array to a constant. Details are a bit hazy. To be quite honest, its been a long time.In the end, I rolled my own kernel modules for DMA transfers. I kept polling at the SGDMA engine's buffer fill levels an enqueue additional transfers as necessary. If you manage to get IRQs working with DMA on Altera's PCIe HIP, please let me know. I couldn't find any Altera literature on this at the time. I tried many different ways, but interrupts just wouldn't propagate through the PCIe HIP.