Multi-master arbitration

[Altera_Forum]

Hi, 

 I have a complex SOPC system with a number of video processing blocks requiring access to DDR2 memory provises by a single HPC DDR2 memory controller. The memory master interface can be divided into realtime and non-realtime interfaces. The realtime interfaces requires a certain gueranteed bandwidth to the DDR2 to keep the video processing chain running, while the non-realtime interfaces should use only the remaining available bandwidth.   I have added pipeline bridges and played around with the arbitration shares in order to ensure that the realtime masters always get the required bandwidth, but I have not been 100% successful. Sometimes a non-realtime master would take up too much bandwidth and the video processing is interrupted.   Most interfaces use bursting and from the Avalon documentation, it is not 100% clear to me if the arbitration shares have any effect on burst-enabled interfaces. If I have, say, four masters accessing a slave and I give one master 4 shares and the other three each 1 share, would the master with 4 shares be permitted four bursts in a row and the other masters one burst each (assuming all interfaces have transactions pending)?   What I need is some way to assign a priority to a master. Is this possible, or should I write my own arbitration logic for that?    Regards, Niki

[Altera_Forum]

i think you should take a look at the Altera multi-port front-end (MPFE) component. you may need to request one of the UDX designs from Altera: 

 http://www.altera.com/support/refdesigns/sys-sol/broadcast/ref-format-conversion-udx3.html

[Altera_Forum]

That MPFE component looks very interesting. I found an interesting online presentation (http://www.slideshare.net/altera/remove-the-external-memory-bottleneck-in-your-video-design) which talks about it. 

 I have a need for priority based arbitration in a video application I am working on as well. Although, the MPFE component seems like it might be overkill for my situation. I really only need two slave ports, one for high priority and one for low priority. I was originally thinking of trying to create my own component for this. Perhaps I should request the reference design from Altera and take a look at it first.  Too bad Altera does not include this functionality as standard in SOPC. There are probably many applications that could benefit from it.

[Altera_Forum]

Hi, 

 Wow! Impressive reference design - I have not seen this one before. I am first going to try to make my own arbitrator since I think it should be fairly simple in my case. But I'll keep this one in mind. Problem with many reference designs are that they do show the full capabilities of the cores / system, but they are typically not commercially viable. I have to do a very similar task than in this reference design, but in a mid range CIII (up to 1080i) - and the customer is already not too happy about the cost of the FPGA. Had to re-write a couple of the standard cores to be specifically efficient for my purpose. Trade development time for lower production cost.   Regards, Niki

[Altera_Forum]

i think the MPFE may become an official component in the future 

  niki, i think you hit the nail on the head with engineering time vs optimization of using any IP versus your own code