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Altera_Forum
Honored Contributor I
1,063 Views

Multiple DDR2 HPC PingPong Scheme

I am using 2 DDR2 HP controller in my design for the pingpong operation. 

ddr2_con ddr2_con_inst_a( 

... 

.phy_clk (dram_clk_a), 

.pll_ref_clk (clk_50m), 

... 

);  

ddr2_con ddr2_con_inst_b( 

... 

.phy_clk (dram_clk_b), 

.pll_ref_clk (clk_50m), 

... 

);  

The pll_ref_clk use the same clock source from external oscillator. All other signals of these 2 ddr2_con use separate signal groups except for reset_n.  

Then I've had 2 FIFOs connected to the both ends(write/read) of the 2 ddr2_con. As the 2 controllers have to share 1 fifo on each end, they have to mux several signals to the fifo, such as phy_clk->fifo's rdclk, local_wdata_req-> fifo's rdreq.  

Becuase the 2 ddr controller have their own pll, phy_clks are from different plls. there is no way not to break the altera recommendation rules. And fifo's rdreq using a muxed signal also seem to violate the Rule S104. 

 

So I am wondering how everyone impeletment multiple ddr controllers and pingpong operation in their designs.
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3 Replies
Altera_Forum
Honored Contributor I
35 Views

No one can help me?

Altera_Forum
Honored Contributor I
35 Views

Hi 

 

I'm currently trying to do very much the same as you do. However, I'm not gating the two clocks, but I intend to merge them. On a standallone trial setup (two independant DR2 HPC with their own example_driver, but phy_clocks merged to one), this worked quite well so far (I'm using Stratix III). Major point is the clock merging instructions. You can find them in an462 (http://www.altera.com.cn/literature/an/an462.pdf), Table 6. If you're not desperate, dont' try to share DLL. 

 

Hope this helps...
Altera_Forum
Honored Contributor I
35 Views

I found that as of 9.0sp2, the clock sharing wasn't exactly perfect. It was easier and safer for me to just edit the generated files and re-generating the pll for the slave device and then share all the static clock manually.  

 

Basically what AN462 says: but you can share all of the static clocks, but not the reconfigurable ones. So, the clock that you use to interface to the ddr blocks will be the same clock domain, but the clock that the actual interface is running on will be different.
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