Multiple UART instantiation

[Altera_Forum]

We have a customer that needs 12 UARTS in his design. Is there a UART core that we can instantiate 12 times in a relatively inexpensive FPGA?

[Altera_Forum]

looks like 12 uarts and a Nios E fit comfortably in an SOPC Builder system on the smallest Cyclone II device (2C5).

[Altera_Forum]

A simple UART (with parity) needs e.g. about 70 logic cells for RxD and 32 for TxD, in addition some logic cells for a baud rate divider, that can be shared by all UART instances. It's just some lines of VHDL code written from the scratch. You'll also find a simple UART design a opencores http://www.opencores.org/projects.cgi/web/uart/overview, some examples have been previously posted at alteraforum.

[Altera_Forum]

i agree about doing it yourself for the resource sharing.

[Altera_Forum]

Probably. There are many different levels of UART, flow control and buffering will add lots of size and complexity. If you just want a dumb 2 wire (TX/RX) interface it would be very small and fit easily on a cheap cyclone.