When I add one (1) NCO from Intel's IP Catalog to my design, the M10K-block usage increases by 576, exceeding the capacity of the Cyclone V device.
The Intel NCO IP Core User Guide states that M10K-block usage for the Cyclone V in the multiplier-based configuration is only 2!
I am using 32-bit phase-accumulator precision and angular resolution, and 24-bit magnitude resolution. Output configuration is dual.
Why is this happening? Thank you.
I suspect that this is happening because the utilization of the memory block is not efficiently used. Can you attach your .qar file so I can reproduce the error? To generate .qar file, go to Project->Archive Project
Can you also let me know which version of Quartus you're using?
In the meantime this thread might help you: https://community.intel.com/t5/Intel-Quartus-Prime-Software/Why-does-infer-Quartus-so-many-M10k-bloc...
I'm able to see that the NCO IP is using 576 M10K blocks.
Can you try using CORDIC generation algorithm instead of multiplier-based to see if it satisfies your requirement even though it has lower FMax.
Can you let me know why you want to use multiplier-based?
The user guide numbers are only for a particular (unspecified) configuration of the NCO.
In multiplier-based architecture, every two bit increment of the angular resolution doubles the required depth of the memories. At 16 bits, only 2 M10Ks are required. So you'll have to reduce the angular resolution to reduce the M10K usage.
Let me know if you have any more querries.
We did not receive any response to the previous answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.