FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5880 Discussions

PCIe "Asynchronous Clock" design on A10 FPGA

JET60200
New Contributor I
176 Views

Hi,

Is there any example design for PCIe HIP that uses asynchronous clock as pcie reference clock in A10 fpga ?

Generally PCIE HIP is required to use the 100 MHz reference clock from the Host PCI Express Connector, which is named as "synchronous clock".   If PCIe uses the 100Mhz on-board reference clock which is "asynchronous clock" system as I know.

 

On our A10 board, we need use that " 100Mhz on-board reference clock from GPS locked Oscillator " ,  where can we find the ref design example ?

 

0 Kudos
2 Replies
KhaiChein_Y_Intel
160 Views

Hi,


Do you mean to connect the refclk pin to internal FPGA generated clock? The input reference clock, refclk, must be stable and free-running at device powerup for a successful device configuration.


Thanks

Best regards,

KhaiY



KhaiChein_Y_Intel
143 Views

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY


Reply