How to properly constrain the PFL for STA

[Knug]

Hi @JohnT_Intel

FPGA_dclk output of the PFL (Parallel Flash Loader). FPGA_dclk is an output of the PFL and gets propagated to my top level wrapper output port. The FPGA_dclk is used normally to configure the FPGA.

How to constrain FPGA_dclk? With an output delay corresponding to the input clock?

I used create_clock command at the input pin (in_clk), the tool should automatically generate the correct FPGA_dclk on the output.

The kit I received for max5 from you specified the following DCLK constraint :

set_output_delay -add_delay -max -clock [get_clocks {clkin_50}] 0.000 [get_ports {fpga_dclk}]
set_output_delay -add_delay -min -clock [get_clocks {clkin_50}] 0.000 [get_ports {fpga_dclk}]

It specified 0.000 output delay. 

Is this right?  No delay at all on the output DCLK?

I had a warning "Min rise delay is equal to max rise delay", if use 0.000

So I used :

create_clock -name {clk} -period 100.000 -waveform { 0.000 50.000 } [get_ports {in_clk}]

# Create the associated virtual input clock
create_clock -name {clk_virt} -period 100.000 -waveform { 0.000 50.000 }

set_output_delay -clock clk_virt \
-max 0.001 \
[get_ports fpga_dclk]

set_output_delay -clock clk_virt \
-min 0.000 \
[get_ports fpga_dclk]

But is this right ?  

Back to my original question. How do I properly constrain DCLK which is currently an output ? Using set_output_delay ? If yes, please comment on the above in bold. What -max (for setup) /   -min (for hold) values can I use?

Regards,

Kevin

[Knug]

Hi @JohnT_Intel

That kit constraints file looks wrong wrt the DCLK constraint. Please comment here.

Wrt the PFL FPGA IP User Guide document this needs to be constrained as a generated clock. I did this.

Reviewing the rest of my wrapper wrt PFL timing constraints.

It lists many false paths and set_max_delay ones for input/output asynchronous signals in the PFL IP user Guide. 

If any issues will get back.

Regards,

Kevin

[Knug]

Need to use set_max_delay constraints for the following wrt PFL IP User guide :

• flash_nce
• flash_addr
• flash_data
• fpga_data

Cannot figure out best set_max_delay values ? to use .  Any help on this will be appreciated.

----

# Output delay (flash_addr, flash_nce) = Distributed timing budget - board delay = Timing budget (major) - board delay from PFL to flash

# Taccess (flash ROM time specification during normal access) = 100ns ? (Table 42 of flash spec tacc ?)
# Timing budget = [roundup(Taccess_pfl/Tpfl_clk) + 1]*Tpfl_clk - Taccess = [roundup(100ns/100ns + 1]*100ns - Taccess = 200ns - Taccess = 200ns - 100ns? = 100ns?

set_max_delay -from [get_ports {in_clk}] -to [get_ports flash_nce] ?
set_max_delay -from [get_ports {in_clk}] -to [get_ports flash_addr[*]] ?

# Read mode (PFL to Flash ROM)
# Input delay (flash_data) = Timing budget (minor) - board delay from flash to PFL
set_max_delay -from [get_ports flash_data[*]] -to [get_ports {in_clk}] ?

# Delay value determined by the board delay and Tsu/Tdh of the FPGA ?

set_output_delay -clock clk_virt -max ? [get_ports fpga_data[*]]

set_output_delay -clock clk_virt -min ? [get_ports fpga_data[*]]

[Knug]

Hi @JohnT_Intel

I am getting confused now !

2 different PFL User Guides with 2 different constraint suggestions! Which one is right ??

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf

flash_nce

set_false_path

flash_addr

set_false_path

flash_data

Normal read mode: set_false_path • Burst read mode: set_input_delay

fpga_data

set_output_delay

fpga_dclk

set_output_delay

-----

https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html

1.4.2.1. Constraining Clock Signal 

1.4.2.2. Constraining Synchronous input and Output ports

1.4.2.3. Constraining Asynchronous input and Output ports and Bidirectional Synchronous ports

1.4.2.4. Summary of PFL Timing constraints

flash_nce

set_max_delay -from pfl_clk -to <port>

flash_addr

set_max_delay -from pfl_clk -to <port>

flash_data

Read mode (PFL to Flash ROM) set_max_delay -from <port> to pfl_clk Write mode (Flash ROM to PFL) set_false_path

fpga_data

set_output_delay -clock fpga_dclk <port>

fpga_dclk

Input clock to DCLK ratio = 1 create_generated_clock -source pfl_clk -invert <fpga_dclk port>

[JohnT_Intel]

Hi,

Normally, the FPGA_dclk signal is not constrain on the delay. The available constrain is input clk to dclk ratio.

Please refer to Table 8 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf

[Knug]

Hi @JohnT_Intel 

That link you sent me lists set_output_delay on the fpga_dclk !

I noticed another doc that lists the fpga_dclk as a generated clk which I constrained.

I sent another message with the differences between the 2 docs which was confusing. Did you see this ?

This lists other PFL constraints too. It states false paths in one of them whereas set_max_delays in the other one. This is confusing. Which one is right?

[Knug]

Hi @JohnT_Intel 

This is what I was talking about :

2 different PFL User Guides with 2 different constraint suggestions! Which one is right ??

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf

flash_nce

set_false_path

flash_addr

set_false_path

flash_data

Normal read mode: set_false_path • Burst read mode: set_input_delay

fpga_data

set_output_delay

fpga_dclk

set_output_delay

-----

https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html

1.4.2.1. Constraining Clock Signal 

1.4.2.2. Constraining Synchronous input and Output ports

1.4.2.3. Constraining Asynchronous input and Output ports and Bidirectional Synchronous ports

1.4.2.4. Summary of PFL Timing constraints

flash_nce

set_max_delay -from pfl_clk -to <port>

flash_addr

set_max_delay -from pfl_clk -to <port>

flash_data

Read mode (PFL to Flash ROM) set_max_delay -from <port> to pfl_clk Write mode (Flash ROM to PFL) set_false_path

fpga_data

set_output_delay -clock fpga_dclk <port>

fpga_dclk

Input clock to DCLK ratio = 1 create_generated_clock -source pfl_clk -invert <fpga_dclk port>

[Knug]

Hi @JohnT_Intel 

I just re-sent the doc differences and it was deleted by the moderator. Why ?

[Knug]

2 different PFL User Guides with 2 different constraint suggestions! Which one is right ??

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf

flash_nce

set_false_path

flash_addr

set_false_path

flash_data

Normal read mode: set_false_path • Burst read mode: set_input_delay

fpga_data

set_output_delay

fpga_dclk

set_output_delay

-----

https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html

1.4.2.1. Constraining Clock Signal 

1.4.2.2. Constraining Synchronous input and Output ports

1.4.2.3. Constraining Asynchronous input and Output ports and Bidirectional Synchronous ports

1.4.2.4. Summary of PFL Timing constraints

flash_nce

set_max_delay -from pfl_clk -to <port>

flash_addr

set_max_delay -from pfl_clk -to <port>

flash_data

Read mode (PFL to Flash ROM) set_max_delay -from <port> to pfl_clk Write mode (Flash ROM to PFL) set_false_path

fpga_data	set_output_delay -clock fpga_dclk <port>
fpga_dclk		Input clock to DCLK ratio = 1 create_generated_clock -source pfl_clk -invert <fpga_dclk port>

[Knug]

Hi @JohnT_Intel 

I just re-sent again the doc differences and it was deleted again by the moderator. Why ?

[Knug]

Hi @JohnT_Intel 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf

https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html

Differences in below constraints between the 2 docs. Which constraints are right ?

flash_nce

flash_addr

flash_data

fpga_data

fpga_dclk 

Hope this message is not removed too.

[Knug]

Why you keep deleting my valid questions ?

Hi @JohnT_Intel 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf

https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html

Differences in below constraints between the 2 docs. Which constraints are right ?

flash_nce

flash_addr

flash_data

fpga_data

fpga_dclk 

[JohnT_Intel]

Hi,

Could you send to me through private message?

[Knug]

Hi @JohnT_Intel 

I generated another ticket with that and it was deleted again. It is important to get the constraints right. What is going on here ?

why there are differences in constraints between the 2 intel docs ??

How do I send a private message? & why my latest messages get deleted ?

What is your private email address ?

Not happy with this matter .

[Knug]

Hi @JohnT_Intel 

I just sent it as a private message. Did you receive it?

[Knug]

Hi @JohnT_Intel 

Did you receive my private message? 

Another query here wrt constraints. Included this within the private message too.

Hope I will receive a reply soon because we will have a review on this with my company later on today and I have to let them know.

--

Neither PFL document listed below lists what constrain to add to the flash_nreset output port of my combined PFL.

I have enabled this extra pin in the PFL IP core & connected it to the reset pin of the flash memory device

Is this pin an Asynchronous output? Can I declare to it   ie   ‘set_false_path -to flash_nreset’ ?

Regards,

Kevin

[Knug]

Hi @JohnT_Intel 

Seen also JTAG signals not constrained.

Timing STA analysis reported following unconstrained :

• no output delay : altera_reserved_tdo
• no input delays : altera_reserved_tms, altera_reserved_tck & alrera_reserved_tdi

How do we constrain them ?

Well editing the ticket now ...

I tried constraining the above jtag signals using input / output delays BUT still see the other issue I have no_clocks reported which I can see its related to the loader Flash programming IP. They popped out 140 of them when I 'check_timing' using the Timing Analyser. Planning to raise a new ticket on this matter!

Few  'Check Timing' No clock listed below :

altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_pgm:pgm|custom_jtag_counter:jtag_addr|data_reg[0]
altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_pgm:pgm|custom_jtag_counter:jtag_addr|data_reg[1]

::::

sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][4]

:::

Many others, 140 in total ...

My top level clock is defined ok.  What internal generated clock I require here ? 

In the other ticket I will include all warnings seen if I can, or should I send them via private message ?

[Knug]

Did you by the way get my private message ? Received no reply to this question yet.

Don't like sending any private messages that will lead nowhere with no reply to them if the recipient has not received them. Please confirm you received my earlier private emails. Thanks 

[Knug]

Hi @JohnT_Intel 

Received no reply to the private messages yet. 

Please let me know that you are looking at those private emails and will receive a reply soon from you or your colleagues to my work email address (you received the private email to) instead of checking here on the Intel community site all the time .

Regards,

Kevin

[Knug]

Hi @JohnT_Intel 

Did you receive those private messages? Received no reply to this question too.

Wondering what is going on. Please let me know if you received them ok ?

This is urgent and need a reply to those emails..

[JohnT_Intel]

Hi,

I have received and have reply to you.