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MAmin
Beginner
1,533 Views

Native Phy Receiver not aligning properly

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Hello

 

I have a Native PHY set to receive a 20 bit pattern for alignment/synchronization of the receiver. I am sending the pattern however when the receiver receives it, it seems like it is aligning it to the MSB locations vs the LSB locations, where it needs to be aligning it.

Here is a screenshot of what I see in simulation.

 

Here is the IP settings for the alignment.

 

 

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1 Solution
CheePin_C_Intel
Employee
69 Views

Hi,

 

From the simulation​, seems like the PCS-core width is 32 bits which I believe you have enable byte SERDES in your transceiver. For your information, if you have byte SERDES enabled, after achieving the word alignment, you would need to perform the byte ordering to get the correct data. For example, from the simulation, seems like the MSByte and LSByte order is swapped.

 

Just would like to check with you which device are you using? For V series devices, they have the byte ordering block supported.

 

Thank you.

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2 Replies
CheePin_C_Intel
Employee
70 Views

Hi,

 

From the simulation​, seems like the PCS-core width is 32 bits which I believe you have enable byte SERDES in your transceiver. For your information, if you have byte SERDES enabled, after achieving the word alignment, you would need to perform the byte ordering to get the correct data. For example, from the simulation, seems like the MSByte and LSByte order is swapped.

 

Just would like to check with you which device are you using? For V series devices, they have the byte ordering block supported.

 

Thank you.

View solution in original post

MAmin
Beginner
69 Views

Hello Cpchan

 

Thanks for the info. I was not aware the V series devices had support for byte ordering.

I looked at the options in the megawizard and I see where it enables it.

 

Thanks

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