Im looking for a clearcut connection integration in between these two IPs. previously with the help of reference designs, i did pcie with ocm and ddr4 sucessfully n verified
Thanks for the reply. I created a design and I configured HBM2 to have only one controller so it exported 2 pseudo channels with the names axi_0 and axi_1 slaves . I connected pcie dma wr master and rd master ports to axi_0 pseudo port of HBM2 and left unconnected axi_1 because i just want to verify(read/write) the 256MB of memory of BOTTOM HBM2 as of now. do u think . is that fine ??