Nios CPU read FIFO

[Altera_Forum]

Hi, all 

 I'm trying to use Nios CPU to read data from a FIFO via Avalon interface. However, when I read data through a pointer which points to the FIFO base address, the data are constant and the data on the output port of FIFO are changing. Could anyone give some hints? How to use the Nios CPU to fetch data form the FIFO? Thanks very much

[Altera_Forum]

You do not provide enough information about your nios design. 

do you have data cache ? let assume your fifo base adr is 0x01000000 then you can try data cache bypass when you set adr bit 31 to 1 and read from adr 0x81000000

[Altera_Forum]

My Nios II CPU has 64kB instruction/data cache since I would like to have a high implementation speed. The burst mode is also enabled. It reads the FIFO data using a pointer which points to the FIFO base address.  

 I will try your suggestion. Thanks! However, I'm confused about the address issue. In my understanding, operating a FIFO has nothing to do with the address.

[Altera_Forum]

the data cache is between nios cpu and your avalon ip (fifo) 

as long as the data cache "thinks" it holds the information last time read from the slave (fifo) it will deliver the value to the cpu instead of reading it again. this ist because your ip modifies its data and therefor is some kind of master that modifies the data, what the cache won't recognise. the data cache bypass with the highest adr bit set is a altera documented workaround. if bit 31 is set then nios will read from the ip directly (bypass the data cache)  so the fifo operations still has nothing to do with the adr. it can be the cache here let me know if it works

[Altera_Forum]

The problem has been solved. Thank you very much!