NiosII and DDR2 simulation issue

[Altera_Forum]

Issue: 

  If the reset location for Nios II is set to the beginning of DDR2(7.2) memory, simulation will fail with some of the Nios signals going unknown.     Why:   During simulation the code for the Nios is automatically loaded into the DDR2 memory model at time = 0us. Then after 200us the DDR2 memory controller starts a training sequence which reads and writes to the first 16 bytes of the DDR2 memory erasing the original contents.     Solution:   In the SOPC Builder offset the reset vector ( in the Nios II component instance) by at least 0x10 and the exception vector should be 0x20 greater then that. This will insure that code is not loaded in the first 16 bytes.     Note: The training sequence takes about 105us. So the system will stall for the first 305us while the memory controller initializes.

[Altera_Forum]

Haha, it is true, the one that you mention is the DDR2(7.2) High Performance controller not the older DDR2 controller (still provided in 7.2). In the old legacy ddr2 controller, user need to specify more timing information in the settings window, but the new DDR2 core use the trainning sequence to adjust the timing automatically by reading and writing to the first few bytes in the memory.