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None of the other write signals get updated even though we have ensured that the waitrequest is low during MSGDMA Simulation


If you could refer to the timing diagram attached, you will see that at t = 960ns a descriptor is issued to the MSGDMA. a few clock cycles later, the read memory mapped master then begins to act upon this request.

The read_address and read_burstcount update correctly, to 0x04000000 and 0x40 respectively for a transfer length of 1KB. 

Once the read request goes low, we assert the read_readdatavalid signal using user logic in our test bench. 

And at t = 1200ns we see that the write_byteenable and write_writedata also update properly. However, none of the other write signals get updated even though we have ensured that the waitrequest is low.


We have verified that the port mappings are the correct width and direction. We have also tried disconnecting the write_write signal from the UUT and the MSGDMA still pulls it low. 

There are warnings like these:

Region: /depth_engine_tb/u0/msgdma_0/dispatcher_internal/the_descriptor_buffers/the_read_command_FIFO/the_dp_ram

# ** Warning: (vsim-3722) simulation/submodules/fifo_with_byteenables.v(128): [TFMPC] - Missing connection for port 'wren_b'.

Any insight into this issue would be greatly appreciated.


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New Contributor II

Hi @EDing​ 


# ** Warning: (vsim-3722) simulation/submodules/fifo_with_byteenables.v(128): [TFMPC] - Missing connection for port 'wren_b'.


The above warning related to the module instantiation. Please check the instantiation of fifo_with_byteenables.v module and "wren_b" port might have not connected or always stuck at 0/1.


With Regards,







According to the Simulation Flow table, since I am simulating a Platform Designer design, the MSGDMA, then I am to follow the steps referred to Creating a System with Platform Designer. I followed the steps outlined in the Advanced System Design Using Platform Designer: Component & System Simulation Tutorial.

I also tried to follow the suggestions outlined under Scripted Simulation Flow. However, the steps say to generate the simulation files from the IP upgrade window and even though the auto upgrade completed successfully, "Generate Simulation Script for IP" button is unavailable. 

Similarly, it is suggested to go to Tools > Generate Simulator Setup Script for IP but that is not visible in my Tools menu.

Moreover, our full Quartus project contains IP and sub modules (like the mac1g) that we do not plan on simulating right now. We can exclude them but I am hoping to find a solution that allows us simulate a sub section of our project. 

Suggestions on how to proceed would be appreciated. 






​Hi HPB,


When I try to trace down these errors, it all comes down to instantiation within these sub modules of Altera Megafunctions. In this case what appears to be the read signal is missing. 

Since these files were output by the Platform Designer software I am hesitant to edit them. 

See attached picture.