I am trying to develop a Simulink model of electric machine with DSP builder advanced blockset. This model will be later used to generate HDL code and loaded into Vector VT System FPGA (Altera Cyclen IV E).
I am able to simulate the system in simulink but when I generate the hardware it says 'Failure to redistribute delay in [IM_Test_User_FPGA] - tight clock constraints'.
I am using an 80 MHz clock.
Kindly let me know how I can tackle this problem.
Hi Athul Mohan,
MATLAB Version 8.6 (R2015b) is not compatible with the Intel Quartus Prime software version 16.1. It supports MathWorks releases R2015a, R2014b.
Can you use the latest release of the software, which is v18.1?
Can you try to reduce the speed and see if you have the same error?
I tried to reduce the clock speed but it gives the same error.
Once I reduce the clock speed below 20 MHz it gives different error - Failure to redistribute delay in [IM_Test_User_FPGA] - negative cycle.
I could see in the Intel page( https://www.intel.com/content/www/us/en/programmable/support/support-resources/intellectual-property... ) that MATLAB Version 8.6 (R2015b) is compatible with the Intel Quartus Prime software version 16.1.
Hi Athul Mohan,
In <Quartus installation directory>/quartus/readme.txt, version 16.1 supports MathWorks releases R2015a, R2014b only. Let me check on this.
Have you try to reduce the speed to a value less than 80 and more than 20?
If I have to use the latest version v18.1, then I have to update the MATLAB Simulink to Version R2016b or above. Currently I have license for only MATLAB 2015b.