FPGA Name: Stratix V FPGA(Part name: 5sgxea7k2f40c2 ;
Board Name: Bittware's S5-PHQ.
Reference Design : Altera PCIe example design for connections and parameter settings
A QSYS with "V Series Avalon MM DMA for PCIe Express" and on-chip memory is build. BAR2 is connected to on-chip memory with clock "coreclkout". Size of on-chip memory = 4096 Bytes, width =32. Instantiate Internal descriptor controller is unchecked but external descriptor controller is not connected in QSYS (i.e. DMA engine is not used).
We would like to perform read and write to on-chip memory through BAR2. When we read or write from host application, sometimes system goes for hang or sometimes we read 0xFF value. The setup that we created in unstable in behavior.
It seem like you are not using Altera Stratix V development kit.
For your information, here is the example design from AlteraWiki:
You may ensure above design is working first, before enable the BAR2 for testing. To further debug this issue, you may need to capture the signaltap for BAR2 to identify the activity happened at the Avalon MM interface to Onchipmemory are expected for memory read or memory write command.
I tried the reference setup given in the above link, it started working i.e., writing into on-chip memory via BAR4 of PCIe. But when I add my custom logic in to the QSYS, I'm facing the similar problem as I faced before(i.e., reading all 0xFF's from the slave interface of my custom logic and than system is going for restart )
custom logic details : Consists of slave interface of data width 32 bits, connected to BAR4 of PCIe. Than I tried to write into register via this slave interface using BAR4, and than I tried to read back from that register(via that slave interface) using BAR4, than I'm reading all 0xFF's and later system is going for restart
I would suggest you to add a signaltap to capture the interface of BAR4 and on-chip memory (good case), and compare against with your custom logic (fail case). It should be able to help to understanding the problem further.