FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

i2c slave in VHDL

Altera Clock Control Block select signal

C model of FFT IP

help needed : upscaling video

FFT Core v9.0 - Help Needed

Does Altera has Logarithm function ip core? HELP..

TSE UDP protocol

Problem with altpll output

Custom Component, Write not working

DAC/ADC configuration issue

SoC Bus for Videoproc. over PCIe

Triple Speed Ethernet

DQ pins limitation of High Performance DDR2 Core

viterbi decoder

FIR filter design in VHDL

Featured Content

Tone Mapping Operator IP Malfunctioning

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Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)