FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

Altera Clock Control Block select signal

C model of FFT IP

help needed : upscaling video

FFT Core v9.0 - Help Needed

Does Altera has Logarithm function ip core? HELP..

TSE UDP protocol

Problem with altpll output

Custom Component, Write not working

DAC/ADC configuration issue

SoC Bus for Videoproc. over PCIe

Triple Speed Ethernet

DQ pins limitation of High Performance DDR2 Core

viterbi decoder

FIR filter design in VHDL

Altera FFT IP-CORE core version 9

Featured Content

Tone Mapping Operator IP Malfunctioning

Unable to simulate DDR3 controller

AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)