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Valued Contributor III
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On Board RAM and Native PHY Transceiver Core

Hello Everyone! 

 

I am trying to implement a transmitter by using Stratix V GT Evaluation Board. I am using 4 channel and 1 Native PHY IPCORE.  

The data which will be transmitted comes from an on board ram which I update it's values from In System Memory Content editor. 

 

My problem is that, when I implement 1 RAM and use the same output on each 4 Channels the transmitter works as expected. However, when I implement 4 rams and use them as an input for each transmitter channel.  

There is 30% bit error rate.  

 

Does anyone have any idea for possible reasons? 

 

So, the one below works. 

tx_pma_parallel_data(79 downto 0)<=ram_q(79 downto 0); 

tx_pma_parallel_data(159 downto 80)<=ram_q(79 downto 0); 

tx_pma_parallel_data(239 downto 160)<=ram_q(79 downto 0); 

tx_pma_parallel_data(319 downto 240)<=ram_q(79 downto 0); 

 

The one below does not work. (in this case each assignment is on a different proccess with each TX_pma clock) 

tx_pma_parallel_data(79 downto 0)<=ram_q(79 downto 0); 

tx_pma_parallel_data(159 downto 80)<=ram_q2(79 downto 0); 

tx_pma_parallel_data(239 downto 160)<=ram_q3(79 downto 0); 

tx_pma_parallel_data(319 downto 240)<=ram_q4(79 downto 0); 

 

 

Kind Regards
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Valued Contributor III
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I believe you mean onchip ram (rather than onboard ram). 

It could be timing problem on mux or memory editor bug or your testing. 

Try mif in each of four rams to bypass editor prblems
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Valued Contributor III
5 Views

 

--- Quote Start ---  

I believe you mean onchip ram (rather than onboard ram). 

It could be timing problem on mux or memory editor bug or your testing. 

Try mif in each of four rams to bypass editor prblems 

--- Quote End ---  

 

 

Hello Kaz, 

 

I actually use MIF to upload to ram. What I do not understand is that how can 1 RAM work while 4 RAM does not? 

 

Kind Regards
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