SRAM ECC : single bit error in 7 bits ECC not detected, cyclone V FPGA.
i have a test to check single bit ECC error detection and correction in SRAM IP. i inject error during write into memory (via encoder logic) and detection shall happen on the read form memory (via decoder logic).
but when i inject single bit error on 7 bit ECC and read the data, i do not see single bit error getting detected. Has anyone seen this issue? Cyclone V FPGA :device : 5CGTFD9E5F35C7 Quartus 14.1 version