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Altera_Forum
Honored Contributor I
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On-chip FIFO in Qsys - How to read/write from/to an SCFIFO?

Hello everyone, 

 

 

I am implementing an MM to MM FIFO in single-clock mode under Qsys. 

Now, I try to understand how to read and write from it. 

 

The API gives the following code for the read and write functions : 

 

Prototype: int altera_avalon_fifo_read_fifo(alt_u32 read_address, alt_u32 ctrl_address) 

Parameters: read_address—the base address of the FIFO read slave 

ctrl_address—the base address of the FIFO control slave 

 

Prototype: int altera_avalon_write_fifo(alt_u32 write_address, alt_u32 ctrl_address, alt_u32 data) 

Parameters: write_address—the base address of the FIFO write slave 

ctrl_address—the base address of the FIFO control slave 

data—the value to write to address offset 0 for Avalon-MM to Avalon-ST transfers, the value to 

write to the single address available for Avalon-MM to Avalon-MM transfers. See the 

Avalon Interface Specifications for the data ordering. 

 

 

I implemented a FIFO without any status port (the datasheet says it is optional). 

But my question is : how to use the read and write functions if I don't have such ports? 

It seems like the needed "ctrl_address" refers to this type of ports. 

 

I could add such a csr port, but on an SCFIFO, it is allowed to do so only on the input side (only the in_csr port is allowed). 

...So it seems like I can at best only write and not read anything. 

 

Does someone have a clear explanation for me ? 

 

 

Thanks a lot, 

Arkady
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