Open Core IP time limited source files expired.

[Altera_Forum]

hi, after using Quartus II 7.0 full version and the NIOS 2 open core plus for a week. I could not synthesize my NIOS 2 system since the cpu.v is a time-limited files. do you guys have this problem? 

 I think I was allowed to use this open core and download the sof file to FPGA and evaluate it as long as my JTAG USB blaster is connected to my PC.

[Altera_Forum]

One option would be to rebuild the system again and see if it starts working. 

 It should just keep working but maybe your time limited license is about to run as as well?  File an SR with the factory and ask them the same question.  It does sound odd to me.

[Altera_Forum]

I agree completely, this should not happen.  

 Try creating a new project from the scratch or copy standard reference design to some other location and try compiling the same. The OCP evaluation should work without any problem.

[Altera_Forum]

this is the error message:  

  Info: Running Quartus II EDA Netlist Writer  Info: Version 7.1 Build 156 04/30/2007 SJ Full Version  Info: Processing started: Tue Jul 24 11:32:08 2007 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off niosbase -c niosbase Error: Can't generate netlist output files because the file "C:/PCIE/niosbase/cpu.v" is an OpenCore Plus time-limited file Error: Can't generate netlist output files because the file "C:/PCIE/niosbase/cpu.v" is an OpenCore Plus time-limited file Error: Can't generate netlist output files because the file "C:/PCIE/niosbase/cpu.v" is an OpenCore Plus time-limited file Error: Can't generate netlist output files because the file "C:/PCIE/niosbase/cpu.v" is an OpenCore Plus time-limited file Error: Quartus II EDA Netlist Writer was unsuccessful. 4 errors, 0 warnings  Info: Allocated 118 megabytes of memory during processing  Error: Processing ended: Tue Jul 24 11:32:10 2007  Error: Elapsed time: 00:00:02 Error: Quartus II Full Compilation was unsuccessful. 4 errors, 112 warnings

[Altera_Forum]

I created a new system with the spec and I got the same problem. Why me!!!!!?????

[Altera_Forum]

Do you use to fake or crack license ? 

 Sometime, Crack License use.....show to error message...

[Altera_Forum]

Hi Dimo 

 I have seen this before with opencore / opencore plus.  The problem you are seeing is because you have 3rd party simulation enabled (hence the EDA netlist writer is running, which is where the error is being seen).   Opencore plus does not allow creation of simulation netlists. Try turning this option off under settings->eda tool settings->simultion. (select no simulator)  If this still doesn't work try removing the PCIE.   Cheers

[Altera_Forum]

OpenCore Plus allows you to run an IP Functional Simulation model in any VHDL or Verilog simulator. It does not allow you to simulate at the gate level. 

 There was a problem found in Quartus 7.1 that exhibited strange behavior for OpenCore Plus. There is a patch available. See http://www.altera.com//support/kdb/solutions/rd07272007_148.html

[Altera_Forum]

The patch is the answer. 

 Install Sp1, then the patch.  An error occored with the Open Core Plus stuff.  By the way, you are using 7.1, not 7.0 as you initially indicated.  Hope all is well.

[Altera_Forum]

problem resolved by unchecking the EDA netlist writer option in simulation setting. My mistake.

[Altera_Forum]

I am using Quartus 2 V8.0. I do not have any of the simulators in the EDA tools and the patch that is available for V7.1 and it doesnt install on the V8.0.

[Altera_Forum]

You should not need any patch for Quartus 8.0. Your post does not say what exactly you are trying to do, nor does it mention any error messages.  

 Can you please clarify exactly what you are trying to do?

[Altera_Forum]

I was just following one of the tutorials on building system using SOPC builder. When I tried using the programmer it said that the file had a few IP core services which uses hardware evaluation and hence I could not program it into the FPGA.  

I am using DE2 kit from Altera and I have not purchased a license.  As soon as I click on the programmer, a dialog box pops up which tells me that the file is time limited.

[Altera_Forum]

What device have you chosen? If you chose a device that has programmer support, you should be able to program the FPGA using the OpenCore Plus hardware evaluation feature for any design that contains Altera IP. You do not need to have a license. OpenCore Plus hardware evaluation is time-limited, but as long as your programmer is connected to your board your design should continue working in hardware. 

 Can you also tell me which IP cores you are using? Perhaps you are using non-Altera IP. Perhaps you should contact Altera technical support. I would guess that you just need some help getting started.

[Altera_Forum]

--- Quote Start ---  I was just following one of the tutorials on building system using SOPC builder. When I tried using the programmer it said that the file had a few IP core services which uses hardware evaluation and hence I could not program it into the FPGA.  I am using DE2 kit from Altera and I have not purchased a license.  As soon as I click on the programmer, a dialog box pops up which tells me that the file is time limited.  --- Quote End ---    You are probably misunderstanding the meaning of the warning messages. The programmer can configure the FPGA with a time-limited SOF.  You should see two warning messages. One is from the assembler. It is telling that it can't generate device programming files. This means it can generate a SOF for configuring the FPGA, but it can't generate a POF for programming a flash device.  The second warning is from the programmer when configuring the FPGA. The warning is telling you that it is a time-limited SOF. This means that the evaluations cores require a permanent link with Quartus programmer, or they would stop working after a certain time.

[Altera_Forum]

dear quartuspenguin, thanks a lot! i had the same problem: 

 Error: Can't generate netlist output files because the file ... is an OpenCore Plus time-limited file  disabled the all EDA tools under EDA Tool Settings --> compilation complete :-)

[Altera_Forum]

--- Quote Start ---  Hi Dimo   I have seen this before with opencore / opencore plus.   The problem you are seeing is because you have 3rd party simulation enabled (hence the EDA netlist writer is running, which is where the error is being seen).    Opencore plus does not allow creation of simulation netlists. Try turning this option off under settings->eda tool settings->simultion. (select no simulator)   If this still doesn't work try removing the PCIE.    Cheers  --- Quote End ---     thank you for your advices, and I try your method ,but it work successfully.However ,I want to ask modelsim for simulation, I can't close the 3rd party simulation , how I can do to solve this problem   Error: Can't generate netlist output files because the file "D:/altera/10.1/quartus/qdesigns/FFT/FFT1/fft-library/asj_fft_wrengen_fft_101.vhd" is an OpenCore Plus time-limited file

[Altera_Forum]

Woohoo.. I had the same issue and was wondering! Thanks for the solution QuartusPenguin.. 

   --- Quote Start ---  Hi Dimo   I have seen this before with opencore / opencore plus.   The problem you are seeing is because you have 3rd party simulation enabled (hence the EDA netlist writer is running, which is where the error is being seen).    Opencore plus does not allow creation of simulation netlists. Try turning this option off under settings->eda tool settings->simultion. (select no simulator)   If this still doesn't work try removing the PCIE.    Cheers  --- Quote End ---