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Overflow issue with building IIR filter using DSP builder basic block

Honored Contributor II

Hi All, 

I'm trying to build a simple IIR filter using Altera DSP builder basic block like delay, gain and adder etc. But the result compare to the block from fdatool are far more worst where it's overflow seems like. Is there anyone knows how to do a quantization in between the adder or multiplier stage to over come this? The below are the matlab script for settign the sample time. 


clock_freq = 300e3; 

sample_time = 1/clock_freq; 

clock_period = 1/(clock_freq*1e-9); 


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